FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20858-4E
FLASH MEMORY
CMOS
8M (1M × 8) BIT
MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12
s FEATURES
• Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection.