MBM29PL160BD

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20872-1E PAGE MODE FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29PL160TD-75/-90/MBM29PL160BD-75/-90 s FEATURES Single 3.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with MASK ROM pinouts 48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin SOP (Package suffix: PF) Minimum 100,000 program/erase cycles High performance 25 ns maximum page access time (75ns maximum random access time) An 8 words page read mode function Sector erase architecture One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase Boot Code Sector Architecture T = Top sector B = Bottom sector Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector Embedded programTM Algorithms Automatically programs and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode Low VCC write inhibit ≤ 2.5 V (Continued) Embedded ...