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74LVT16500A Dataheets PDF



Part Number 74LVT16500A
Manufacturers NXP
Logo NXP
Description 3.3V 18-bit universal bus transceiver
Datasheet 74LVT16500A Datasheet74LVT16500A Datasheet (PDF)

74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Rev. 03 — 29 May 2006 Product data sheet 1. General description The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For .

  74LVT16500A   74LVT16500A


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74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Rev. 03 — 29 May 2006 Product data sheet 1. General description The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary.


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