TH58NVG1S3AFT05

TH58NVG1S3AFT05 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2GBIT (256M u 8BITS) CMOS NAND E2PROM DESCRIPTION The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density nonvolatile memory data storage. FEATURES x Organization Memory cell allay 2112 u 64K u 8 u 2 Register 2112 u 8 Page size 2112bytes Block size (128K  4K) bytes x Modes ReadResetAuto Page Program Auto Block EraseStatus Read x Mode control Serial inputoutput Command control x Powersupply x Program/Erase Cycles x Access time Cell array to register Serial Read Cycle x Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby x Package TSOP I 48-P-1220-0.50 (Weight : 0.53 g typ.) VCC 2...