SCD1283

CD1283 IEEE 1284-Compatible Parallel Interface Datasheet Product Features Parallel Port (Peripheral-side) s s High-speed, bidirectional, multi-protocol parallel port: s Hardware implementation of all modes of the IEEE STD (Standard) 1284 specification (including automatic negotiation) — Centronics-compatible mode — Reverse Byte mode — Reverse Nibble mode — ECP (extended capabilities port) mode with run-length encoding/decoding — EPP (enhanced parallel port) mode — Up to 2-Mbytes/sec. transfer rate in ECP and EPP modes s 64-byte parallel FIFO with DMA interface — 64-byte FIFO can accommodate up to 4 Kbytes of compressed data with RLE (run-length encoded) compression enabled s s Supports peripheral-side operation Data and control input/output pads support IEEE STD1284 level-2 interface specification CPU bus interface — High-speed slave DMA handshake interface — Three clocks per word DMA transfers — On-the-fly data compression using RLE (run-length encoded) encoding and decoding 8/16-bit data interface — BYTESWAP input provides easy interface to both Big- and Little-Endian systems — Vectored interrupts simplify interrupt service routines System clock up to 25 MHz CMOS technology enables high speed and low power Available in a 100-pin MQFP package General s s s As of May 2001, this document replaces the Basis Communications Corp. document CL-CD1283 — IEEE 1284-Compatible Parallel Interface. May 2001 Information in this document is provided in connection with Intel® pro...