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SDA5553 Dataheets PDF



Part Number SDA5553
Manufacturers Micronas Semiconductor
Logo Micronas Semiconductor
Description SDA55xx TVText Pro
Datasheet SDA5553 DatasheetSDA5553 Datasheet (PDF)

DATA SHEET MICRONAS SDA 55xx TVText Pro Edition Sept. 10, 2004 6251-556-3DS MICRONAS SDA 55xx Contents Page 8 8 8 8 9 9 9 9 11 12 12 12 12 13 13 14 14 14 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 18 18 18 19 19 20 20 20 20 20 20 20 21 Section 1. 1.1. 1.1.1. 1.1.2. 1.1.3. 1.1.4. 1.1.5. 1.1.6. 1.2. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.2. 2.2.1. 2.2.2. 2.2.2.1. 2.2.2.1.1. 2.2.2.1.2. 2.2.2.1.3. 2.2.2.2. 2.2.3. 2.2.4. 2.2.4.1. 2.2.4.1.1. 2.2.4.1.2. 2.2.4.1.3. 2.2.4.1.4. 2.2.4.1.5. 2.2.4.2. 2.

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DATA SHEET MICRONAS SDA 55xx TVText Pro Edition Sept. 10, 2004 6251-556-3DS MICRONAS SDA 55xx Contents Page 8 8 8 8 9 9 9 9 11 12 12 12 12 13 13 14 14 14 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 18 18 18 19 19 20 20 20 20 20 20 20 21 Section 1. 1.1. 1.1.1. 1.1.2. 1.1.3. 1.1.4. 1.1.5. 1.1.6. 1.2. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.2. 2.2.1. 2.2.2. 2.2.2.1. 2.2.2.1.1. 2.2.2.1.2. 2.2.2.1.3. 2.2.2.2. 2.2.3. 2.2.4. 2.2.4.1. 2.2.4.1.1. 2.2.4.1.2. 2.2.4.1.3. 2.2.4.1.4. 2.2.4.1.5. 2.2.4.2. 2.2.4.3. 2.2.5. 2.2.5.1. 2.2.5.1.1. 2.2.5.1.2. 2.2.6. 2.2.7. 2.2.8. 2.2.8.1. 2.2.8.1.1. 2.2.8.1.2. 2.2.8.1.3. 2.2.8.1.4. 2.2.8.1.5. Title Introduction General Features External Crystal and Programmable Clock Speed Microcontroller Features Memory Display Features Acquisition Features Ports Overview of Current Versions and Packages for SDA 55xx Functional Description Clock System General Function System Clock Pixel Clock Related Registers Slicer and Data Acquisition General Function Slicer Architecture Distortion Processing Noise Frequency Attenuation Group Delay Data Separation H/V-Synchronization Acquisition Interface Framing Code Check Framing Code FC1 Framing Code FCVPS Framing Code FC3 Framing Code FCWSS FC Check Select Interrupts VBI Buffer and Memory Organization Related Registers RAM Registers Field Parameters Line Parameters Recommended Parameter Settings Microcontroller Architecture CPU Hardware Instruction Decoder Program Control Section Internal Data RAM Arithmetic/Logic Unit (ALU) Boolean Processor DATA SHEET 2 Sept. 10, 2004; 6251-556-3DS Micronas DATA SHEET SDA 55xx Contents, continued Page 21 21 22 22 22 23 23 23 23 23 23 25 26 26 26 27 32 37 37 37 37 38 38 38 39 39 40 41 41 41 41 41 42 42 43 44 44 44 45 45 45 45 46 46 46 46 46 Section 2.2.8.1.6. 2.2.8.1.7. 2.2.8.1.8. 2.2.8.2. 2.2.8.3. 2.2.8.3.1. 2.2.8.3.2. 2.2.8.3.3. 2.2.8.3.4. 2.2.8.3.5. 2.2.9. 2.2.9.1. 2.2.10. 2.2.10.1. 2.2.10.2. 2.2.10.3. 2.2.10.4. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.4.1. 2.3.5. 2.3.6. 2.3.6.1. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 2.3.12. 2.3.13. 2.3.14. 2.3.15. 2.3.16. 2.3.17. 2.3.18. 2.3.19. 2.3.20. 2.3.21. 2.3.22. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. Title Program Status Word Register (PSW) Stack Pointer (SP) Data Pointer Register (DPTR). CPU Timing Addressing Modes Register Addressing Direct Addressing Register Indirect Addressing Immediate Addressing Base Register plus Index Register Indirect Addressing Ports and I/O-Pins Read Modify Write Feature Instruction Set Notes on Data Addressing Modes Notes on Program Addressing Modes Instruction Set Description Instruction Opcodes in Hexadecimal Order Interrupt Interrupt System Interrupt Sources Overview Enabling Interrupts Interrupt Enable Registers (IEN0, IEN1, IEN2, IEN3) Interrupt Source Registers Interrupt Priority Interrupt Priority Registers (IP0 IP1) Interrupt Vectors Interrupt and Memory Extension Interrupt Handling Interrupt Latency Interrupt Flag Clear Interrupt Return Interrupt Nesting External Interrupts Extension of Standard 8051 Interrupt Logic Interrupt Task Function Power Saving Modes Power-Save Mode Registers Idle Mode Power-down Mode Power-save Mode Slow-Down Mode Reset Reset Sources Reset Filtering Reset Duration Registers Micronas Sept. 10, 2004; 6251-556-3DS 3 SDA 55xx Contents, continued Page 46 46 46 46 46 46 46 46 47 47 48 48 48 48 48 48 48 48 49 49 49 50 50 50 50 50 50 50 50 50 50 50 50 50 50 51 51 51 51 51 51 51 52 52 53 53 53 Section 2.4.5. 2.4.6. 2.4.7. 2.4.8. 2.4.9. 2.4.10. 2.4.10.1. 2.4.10.2. 2.5. 2.5.1. 2.5.2. 2.5.2.1. 2.5.2.1.1. 2.5.2.1.2. 2.5.2.1.3. 2.5.2.1.4. 2.5.2.2. 2.5.2.2.1. 2.5.3. 2.5.3.1. 2.5.3.2. 2.5.4. 2.5.4.1. 2.5.4.2. 2.5.4.2.1. 2.5.4.2.2. 2.5.4.2.3. 2.5.4.2.4. 2.5.4.2.5. 2.5.4.3. 2.5.4.3.1. 2.5.4.4. 2.5.4.5. 2.5.4.6. 2.5.4.7. 2.5.4.7.1. 2.5.4.8. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2. 2.6.1.3. 2.6.1.4. 2.6.2. 2.7. 2.7.1. 2.7.1.1. Title Functional Blocks RAMs Analog Blocks Microcontroller Ports Initialization Phase Acquisition Display Memory Organization Program Memory Internal Data RAM CPU RAM Address Space Registers Bit Addressable RAM Area Stack Extended Data RAM (XRAM) Extended Data Memory Address Mapping Memory Extension Memory Extension Registers Reset Value Instructions on which Memory Extension would act Program Memory Banking (LJMP) MOVC Handling MOVC with Current Bank MOVC with Memory Bank MOVX Handling MOVX with Current Bank MOVX with Data Memory Bank CALLs and Interrupts Memory Extension Stack Stack Full Timing Interfacing Extended Memory Application Examples Sample Code ROM and ROMless Version UART Operation Modes of the UART Mode 0 Mode 1 Mode 2 Mode 3 Multiprocessor Communication General Purpose Timers/Counters Timer/Counter 0: Mode Selection Mode 0 DATA SHEET 4 Sept. 10, 2004; 6251-556-3DS Micronas DATA SHEET SDA 55xx Contents, continued Page 53 53 53 53 53 53 54 54 55 55 55 55 55 55 55 55 55 56 56 56 56 56 56 57 57 57 59 59 59 59 59 59 60 60 61 61 62 63 63 63 63 63 63 63 64 65 65 Section 2.7.1.2. 2.7.1.3. 2.7.1.4. 2.7.2.


FQBI9N50 SDA5553 TCA955


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