ICS9248-107

Integrated Circuit Systems, Inc. ICS9248-107 Frequency Timing Generator for PENTIUM II Systems Recommended Application: RCC chipset Output Features: 4 - CPUs @ 2.5V, up to 180MHz. 3 - IOAPIC @ 2.5V 3 - 3V66MHz @ 3.3V. 11 - PCIs @ 3.3V 1 - 48MHz, @ 3.3V fixed 1 - 24/48MHz, @ 3.3V Features: Up to 180MHz frequency support Use a zero delay buffer such as the ICS9179-06 to generate SDRAM clocks. Support power management: Power down Mode from I2C programming. Spread spectrum for EMI control ± 0.25% center spread). Uses external 14.318MHz crystal 5 - FS pins for frequency select Pin Configuration GNDREF REF0 *SEL24_48#/REF1 VDDREF X1 X2 GNDPCI *FS0/PCICLK_F *FS1/PCICLK1 VDDPCI *FS2/PCICLK2 *FS3/PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PCICLK8 PCICLK9 PCICLK10 VDDPCI PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDLAPIC IOAPIC0 IOAPIC1 GNDLAPIC IOAPIC2 VDDLCPU CPUCLK0 GNDLCPU CPUCLK1 VDDLCPU CPUCLK2 CPUCLK3 GNDLCPU VDD66 3V66_0 3V66_1 3V66_2 GND66 SDATA 2 I C SCLK ICS9248-107 { VDD48 48MHz/FS4* 24_48MHz GND48 48-pin SSOP *120K ohm pull-up to VDD on indicated inputs. Key Specifications: CPU Output Jitter: <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps PLL2 Block Diagram 48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 24_48MHz CPU Output Skew: <175ps IOAPIC Output Ske...