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ICS9248-98 Dataheets PDF



Part Number ICS9248-98
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frequency Generator & Integrated Buffers
Datasheet ICS9248-98 DatasheetICS9248-98 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9248-98 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 440BX/VIA Apollo 133 style chipset. Output Features: • 2 - CPUs @2.5V, up to 166MHz. • 1 - IOAPIC @ 2.5V • 13 - SDRAM @ 3.3V • 6 - PCI @3.3V, • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support power management: PCI, CPU stop and Mode • Spread spectrum for EMI control (0 to -0.5%, ± 0.25%)..

  ICS9248-98   ICS9248-98



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Integrated Circuit Systems, Inc. ICS9248-98 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 440BX/VIA Apollo 133 style chipset. Output Features: • 2 - CPUs @2.5V, up to 166MHz. • 1 - IOAPIC @ 2.5V • 13 - SDRAM @ 3.3V • 6 - PCI @3.3V, • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support power management: PCI, CPU stop and Mode • Spread spectrum for EMI control (0 to -0.5%, ± 0.25%). • Uses external 14.318MHz crystal Skew Specifications: • CPU – CPU: <175ps • SDRAM - SDRAM: <250ps • PCI – PCI: <500ps • BUFFER_IN-SDRAM: <5ns • CPU(early)-PCI: Min=1.0ns, Typ=2.3ns, Max=4.0ns Pin Configuration VDD1 *PCI_STOP/REF0 GND X1 X2 VDD2 *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFER IN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1/FS2* GND CPUCLK_F CPUCLK1 VDDL2 CLK_STOP#* SDRAM_F GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24MHz/FS1* * Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND 48-Pin 300mil SSOP Block Diagram PLL2 /2 X1 X2 BUFFER IN XTAL OSC 48MHz 24MHz IOAPIC REF(1:0) CPUCLK_F PLL1 Spread Spectrum FS(3:0) 4 MODE STOP Functionality FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 80.00 75.00 83.31 66.82 103.00 112.01 68.01 100.23 120.00 114.99 109.99 105.00 140.00 150.00 124.00 132.99 PCICLK (MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25 STOP 2 CPUCLK 1 LATCH STOP 12 SDRAM (11:0) SDRAM_F 4 POR CLK_STOP# PCI_STOP# SDATA SCLK Control Logic Config. Reg. PCI CLOCK DIVDER STOP 5 PCICLK (4:0) PCICLKF 9248-98 Rev D 11/6/00 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-98 ICS9248-98 Pin Descriptions PIN NUMBER 1 2 3,9,16,22, 33,39,45 4 5 6,14 7 MODE1, 2 FS3 8 13, 12, 11, 10 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 27 40 41 42 43 44 46 47 48 PCICLK0 PCICLK (4:1) BUFFER IN SDRAM (11:0) VDD3 SDATA SCLK 24MHz FS1 1, 2 P I N NA M E VDD1 REF0 PCI_STOP#1 GND X1 X2 VDD2 PCICLK_F TYPE DESCRIPTION P W R REF, XTAL power supply, nominal 3.3V O U T 14.318 Mhz reference clock. Halts PCICLK clocks at logic 0 level, when input low IN (In mobile mode, MODE=0) PWR IN OUT PWR OUT IN IN OUT OUT IN OUT PWR I/O IN OUT IN OUT IN PWR OUT IN PWR OUT OUT OUT IN OUT PWR Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Supply for PCICLK_F and PCICLK, nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CLK_STOP# This asynchronous input halts CPUCLK, IOAPIC & SDRAM clocks at logic "0" level when driven low. Supply for CPU clocks 2.5V nominal CPU clock outputs, powered by VDDL2. Low if CLK_STOP# = Low Free running CPU clock. Not affected by the CLK_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L 1 . Supply for IOAPIC, 2.5V nominal 48MHz FS01, 2 VDD4 SDRAM_F CLK_STOP# VDDL2 CPUCLK1 CPUCLK_F REF1 FS21, 2 I OA P I C VDDL1 Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. Third party brands and names are the property of their respective owners. 2 ICS9248-98 General Description The ICS9248-98 is a single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system. .


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