K4H561638F-TCCC

DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM 256Mb F-die DDR400 SDRAM Specification Revision 1.1 Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) 256Mb F-die Revision History Revison 1.0 (June. 2003) 1. First release Revison 1.1 (August. 2003) 1. Added x8 org (K4H560838F) DDR SDRAM Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Key Features 200MHz Clock, 400Mbps data rate. VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input LDM,UDM for write masking only (x16) Auto & Self refresh 7.8us refresh interval(8K/64ms refresh) Maximum burst refresh cycle : 8 66pin TSOP II package DDR SDRAM Ordering Information Part No. K4H560838F-TCCC K4H560838F-TCC4 K4H561638F-TCCC K4H561638F-TCC4 16M x 16 32M x 8 Org. Max Freq. CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3) SSTL2 66pin TSOP II Interface SSTL2 Package 66pin TSOP II Operating Frequencies - CC(DDR400@CL=3) Speed @CL3 CL-tRCD-...