CY7C09379

25/0251 CY7C09279/89 CY7C09379/89 32K/64K x16/18 Synchronous Dual Port Static RAM Features True dual-ported memory cells which allow simultaneous access of the same memory location Six Flow-Through/Pipelined devices — 32K x 16/18 organization (CY7C09279/379) — 64K x 16/18 organization (CY7C09289/389) Three Modes — Flow-Through — Pipelined — Burst Pipelined output mode on both ports allows fast 100MHz cycle time 0.35-micron CMOS for optimum speed/power High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) Fully synchronous interface for easier operation Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and Lower Byte Controls for Bus Matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT70927 and IDT709279 Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL OEL 1 0/1 1 0/1 0 0 CE0R CE1R LBR OER FT/PipeL [2] 0/1 1b 0b 1a 0a b a 0a 1a 0b 1b a b 0/1 FT/PipeR 8/9 [2] 8/9 I/O8/9L–I/O15/17L [3] I/O8/9R–I/O15/17R 8/9 15/16 I/O Control I/O Control 8/9 15/16 I/O0L–I/O7/8L A0L–A14/15L CLKL ADSL CNTENL CNTRSTL [4] I/O0R–I/O7/8R Counter/ Address Register Decode Counter/ Address Register Decode A0R–A14/15R CLKR ADSR CNTENR CNTRST...