(CY7C09159 / CY7C09169) 8K/16K x 9 Synchronous Dual-Port Static RAM
51
fax id: 5218
PRELIMINARY
CY7C09159 CY7C09169
8K/16K x 9 Synchronous Dual-Port Static RAM
Features
• True Dual-Por...
Description
51
fax id: 5218
PRELIMINARY
CY7C09159 CY7C09169
8K/16K x 9 Synchronous Dual-Port Static RAM
Features
True Dual-Ported memory cells which allow simultaneous access of the same memory location 2 Flow-Through/Pipelined devices — 8K x 9 organization (CY7C09159) — 16K x 9 organization (CY7C09169) 3 Modes — Flow-Through — Pipelined — Burst Pipelined output mode on both ports allows fast 100-MHz cycle time 0.35-micron CMOS for optimum speed/power
v
High-speed clock to data access 6.5/7.5/12 ns (max.) Low operating power — Active= 200 mA (typical) — Standby= 0.05 mA (typical) Fully synchronous interface for easier operation Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL OEL R/WR OER
CE0L CE1L
1
0/1
1
0/1
0
0
CE0R CE1R
FT/PipeL I/O0L–I/O8L
0/1
1
0
0
1
0/1
FT/PipeR I/O0R–I/O8R
9
9
I/O Control
[1]
I/O Control
13/14
[1]
13/14
A0–A12/13L CLKL ADSL CNTENL CNTRSTL
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0–A12/13R CLKR ADSR CNTENR CNTRSTR
Note: 1. A0–A12 for 8K; A0–A13 for 16K.
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Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 ...
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