Document
Features
• 80C51 Core Architecture • 256 Bytes of On-chip RAM • 1K Bytes of On-chip XRAM • 32K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C Erase/Write Cycle: 100K
• Boot Code Section with Independent Lock Bits • 2K Bytes of On-chip Flash for Bootloader • In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability • 2K Bytes of On-chip EEPROM
Erase/Write Cycle: 100K • 14-sources 4-level Interrupts • Three 16-bit Timers/Counters • Full Duplex UART Compatible 80C51 • Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz) • Five Ports: 32 + 2 Digital I/O Lines • Five-channel 16-bit PCA with:
– PWM (8-bit) – High-speed Output – Timer and Edge Capture • Double Data Pointer • 21-bit Watchdog Timer (7 Programmable Bits) • A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs • Full CAN Controller: – Fully Compliant with CAN Rev2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 15 Independent Message Objects:
Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt – Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode – 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode – Readable Error Counters – Programmable Link to On-chip Timer for Time Stamping and Network Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling • On-chip Emulation Logic (Enhanced Hook System) • Power Saving Modes: – Idle Mode – Power-down Mode
1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory
T89C51CC01 AT89C51CC01
Rev. 4129N–CAN–03/08
1
• Power Supply: 3V to 5.5V • Temperature Range: Industrial (-40° to +85°C) • Packages: VQFP44, PLCC44
Description
The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications.
In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 1.2-Kbyte RAM.
Special attention is paid to the reduction of the electro-magnetic emission of T89C51CC01.
Block Diagram
RxD TxD Vcc Vss ECI PCA T2EX T2 RxDC TxDC
XTAL1 XTAL2
ALE PSEN
EA
RD WR
CPU
UART
RAM 256x8
Flash Boot EE XRAM
32kx loader PROM 1kx8 8 2kx8 2kx8
C51 CORE
IB-bus
PCA Timer 2
CAN
CONTROLLER
Timer 0 Timer 1
INT Ctrl
Parallel I/O Ports and Ext. Bus Watch Dog
Port 0Port 1 Port 2 Port 3 Port 4
10 bit ADC
RESET T0 T1
INT0 INT1
P0 P1(1)
P2 P3 P4(2) VAREF VAVCC VAGND
Notes: 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port
2 A/T89C51CC01
4129N–CAN–03/08
Pin Configuration
A/T89C51CC01
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2
6 5 4 3 2 1 44 43 42 41 40
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4
EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1
P3.4/T0 P3.5/T1
7 8 9 10 11 12 13 14 15 16 17
PLCC44
39 ALE 38 PSEN 37 P0.7/AD7 36 P0.6/AD6 35 P0.5/AD5 34 P0.4/AD4 33 P0.3/AD3 32 P0.2/AD2 31 P0.1/AD1 30 P0.0/AD0 29 P2.0/A8
P3.6/WR 18 P3.7/RD 19 P4.0/ TxDC 20 P4.1/RxDC 21 P2.7/A15 22 P2.6/A14 23 P2.5/A13 24 P2.4/A12 25 P2.3/A11 26 P2.2/A10 27 P2.1/A9 28
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2
4129N–CAN–03/08
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4
EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1
P3.4/T0 P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6
VQFP44
28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P0.0 /AD0 P2.0/A8
P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
3
I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred .