Document
Features
• 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K • Boot Code Section with Independent Lock Bits • 2K Bytes of On-chip Flash for Bootloader • In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability • 2K Bytes of On-chip EEPROM – Erase/Write Cycle: 100K • 14-sources 4-level Interrupts • Three 16-bit Timers/Counters • Full Duplex UART Compatible 80C51 • Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz) • Three or Four Ports: 16 or 20 Digital I/O Lines • Two-channel 16-bit PCA – PWM (8-bit) – High-speed Output – Timer and Edge Capture • Double Data Pointer • 21-bit Watchdog Timer (7 Programmable bits) • A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs • Full CAN Controller – Fully Compliant with CAN rev.# 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 4 Independent Message Objects
-Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature) -Priority Management for Transmission -Message Object Overrun Interrupt – Supports -Time Triggered Communication -Autobaud and Listening Mode -Programmable Automatic Reply Mode • 1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode • Readable Error Counters • Programmable Link to On-chip Timer for Time Stamping and Network Synchronization • Independent Baud Rate Prescaler • Data, Remote, Error and Overload Frame Handling • Power-saving Modes – Idle Mode – Power-down Mode • Power Supply: 3 Volts to 5.5 Volts • Temperature Range: Industrial (-40° to +85°C) • Packages: SOIC28, SOIC24, PLCC28, VQFP32
Note: 1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit Microcontroller with CAN Controller and Flash
T89C51CC02 AT89C51CC02
Rev. 4126L–CAN–01/08
Description Block Diagram
Part of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.
In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM.
Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02.
RxD TxD Vcc Vss ECI PCA T2EX T2 RxDC TxDC
XTAL1 XTAL2
CPU
UART
RAM 256x8
Flash Boot EE XRAM
16K x loader PROM 256 x 8 8 2K x 8 2K x 8
C51 CORE
IB-bus
PCA Timer 2
CAN
CONTROLLER
Timer 0 Timer 1
INT Ctrl
Parallel I/O Ports Port 1 Port 2 Port 3Port 4
Watch Dog
10-bit ADC
RESET T0 T1
INT0 INT1 P1(1) P2(2)
P3 P4(2) VAREF VAVCC VAGND
Note: 1. 8 analog Inputs/8 Digital I/O. 2. 2-bit I/O Port.
2 AT/T89C51CC02
4126L–CAN–01/08
Pin Configurations
VAREF VAGND VAVCC P4.1/RxDC P4.0/TxDC
P2.1 P3.7 P3.6 P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0
P3.1/TxD
P3.0/RxD
1 2 3 4 5 6 7 8 9 10 11 12
13
14
SO28
28 P1.0/AN0/T2 27 P1.1/AN1/T2EX 26 P1.2/AN2/ECI 25 P1.3/AN3/CEX0
24 P1.4/AN4/CEX1 23 P1.5/AN5 22 P1.6/AN6 21 P1.7/AN7 20 P2.0
19 RESET 18 VSS 17 VCC
16 XTAL1
15 XTAL2
AT/T89C51CC02
VAREF 1
VAGND 2
VAVCC 3 P4.1/RxDC 4 P4.0/TxDC 5
P3.5/T1 6 P3.4/T0 7 P3.3/INT1 8 P3.2/INT0 9 P3.1/TxD 10 P3.0/RxD 11
XTAL2 12
SO24
24 P1.0/AN0/T2
23 P1.1/AN1/T2EX 22 P1.2/AN2/ECI 21 P1.3/AN3/CEX0
20 P1.4/AN4/CEX1 19 P1.5/AN5 18 P1.6/AN6 17 P1.7/AN7 16 RESET
15 VSS 14 VCC
13 XTAL1
P4.1/RxDC VAVCC VAGND VAREF P1.0/AN 0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI
4 3 2 1 28 27 26
P4.0/TxDC P2.1 P3.7 P3.6
P3.5/T1 P3.4/T0 P3.3/INT1
5 6 7 8 9 10 11
PLCC-28
25 P1.3/AN3/CEX0 24 P1.4/AN4/CEX1 23 P1.5/AN5 22 P1.6/AN6 21 P1.7/AN7 20 P2.0 19 RESET
P3.2/INT0 12 P3.1/TxD 13 P3.0/RxD 14 XTAL2 15 XTAL1 16 VCC 17 VSS 18
4126L–CAN–01/08
3
P4.1/RxDC VAVCC NC VAGND VAREF P1.0/AN 0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI
32 31 30 29 28 27 26 25
P4.0/TxDC P2.1 P3.7 P3.6
P3.5/T1 P3.4/T0
NC P3.3/INT1
1 2
3 4 5 6 7 8
QFP-32
24 P1.3/AN3/CEX0 23 P1.4/AN4/CEX1
22 P1.5/AN5 21 P1.6/AN6 20 P1.7/AN7 19 P2.0 18 NC 17 RESET
P3.2/INT0 9 P3.1/TxD 10 P3.0/RxD 11
NC 12 XTAL2 13 XTAL1 14
VCC 15 VSS 16
4 AT/T89C51CC02
4126L–CAN–01/08
AT/T89C51CC02
Pin Description
Pin Name
VSS VCC VAREF VAVCC VAGND P1.0:7
P2.0:1
Type
GND I/O
I/O
Description
Circuit ground
Supply Voltage
Reference Voltage for ADC (input)
Supply Voltage for ADC
Reference Ground for ADC (internaly connected with the VSS)
Port 1: Is an.