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MC74VHC1G01 Dataheets PDF



Part Number MC74VHC1G01
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 2-Input NAND Gate
Datasheet MC74VHC1G01 DatasheetMC74VHC1G01 Datasheet (PDF)

Single 2-Input NAND Gate with Open Drain Output MC74VHC1G01, MC74VHC1GT01 The MC74VHC1G01 / MC74VHC1GT01 is a 2−input NAND gate with an open drain output in tiny footprint packages. The MC74VHC1G01 has CMOS−level input thresholds while the MC74VHC1GT01 has TTL−level inputs. The input structures provide protection when voltages up to 5.5 V are applied, regardless of the supply voltage. This allows the device to be used to interface 5 V circuits to 3 V circuits. Some output structures also provi.

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Single 2-Input NAND Gate with Open Drain Output MC74VHC1G01, MC74VHC1GT01 The MC74VHC1G01 / MC74VHC1GT01 is a 2−input NAND gate with an open drain output in tiny footprint packages. The MC74VHC1G01 has CMOS−level input thresholds while the MC74VHC1GT01 has TTL−level inputs. The input structures provide protection when voltages up to 5.5 V are applied, regardless of the supply voltage. This allows the device to be used to interface 5 V circuits to 3 V circuits. Some output structures also provide protection when VCC = 0 V and when the output voltage exceeds VCC. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, SC−74A, TSOP−5, SOT−553, SOT−953 and UDFN6 Packages • Chip Complexity < 100 FETs • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant A B & Y Figure 1. Logic Symbol DATA SHEET www.onsemi.com SC−88A DF SUFFIX CASE 419A MARKING DIAGRAMS XX MG G SC−74A DBV SUFFIX CASE 318BQ XXX MG G 5 1 TSOP−5 DT SUFFIX CASE 483 5 XX MG G 1 5 XXXAYWG G 1 SOT−553 XV5 SUFFIX CASE 463B XX MG G SOT−953 P5 SUFFIX CASE 527AE XM 1 UDFN6 1.45 x 1.0 XM 1 CASE 517AQ UDFN6 1.0 x 1.0 CASE 517BX XM 1 XX = Specific Device Code M = Date Code* A = Assembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2011 1 April, 2022 − Rev. 20 Publication Order Number: MC74VHC1G01/D MC74VHC1G01, MC74VHC1GT01 B 1 A 2 GND 3 VCC 5 OVT Y 4 (SC−88A/SOT−553/ TSOP−5/ SC−74A) PIN ASSIGNMENT (SC−88A/SOT−553/ TSOP−5/SC−74A) Pin Function 1 B 2 A 3 GND 4 Y 5 VCC A 1 GND 2 B 3 VCC 5 OVT Y 4 SOT−953 Figure 2. Pinout (Top View) PIN ASSIGNMENT (SOT−953) Pin Function 1 A 2 GND 3 B 4 Y 5 VCC FUNCTION TABLE Input A B L L L H H L H H Output Y Z Z Z L B1 A2 6 VCC OVT 5 NC GND 3 UDFN6 4Y PIN ASSIGNMENT (UDFN) Pin Function 1 B 2 A 3 GND 4 Y 5 NC 6 VCC www.onsemi.com 2 MC74VHC1G01, MC74VHC1GT01 MAXIMUM RATINGS Symbol Characteristics Value Unit VCC DC Supply Voltage TSOP−5, SC−88A (NLV) −0.5 to +7.0 V SC−74A, SC−88A, UDFN6, SOT−553, SOT−953 −0.5 to +6.5 VIN DC Input Voltage TSOP−5, SC−88A (NLV) −0.5 to +7.0 V SC−74A, SC−88A, UDFN6, SOT−553, SOT−953 −0.5 to +6.5 VOUT DC Output Voltage (NLV) 1Gxx −0.5 to VCC + 0.5 V 1GTxx Active−Mode (High or Low State) Tri−State Mode (Note 1) Power−Down Mode (VCC = 0 V) −0.5 to VCC + 0.5 −0.5 to +7.0 −0.5 to +7.0 DC Output Voltage Active−Mode (High or Low State) −0.5 to VCC + 0.5 V Tri−State Mode (Note 1) −0.5 to +6.5 Power−Down Mode (VCC = 0 V) −0.5 to +6.5 IIK IOK IOUT ICC or IGND TSTG TL TJ qJA DC Input Diode Current DC Output Diode Current (NLV) 1Gxx 1GTxx DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin or Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 secs Junction Temperature Under Bias Thermal Resistance (Note 2) VIN < GND VOUT > VCC, VOUT < GND VOUT < GND VOUT < GND SC−88A SC−74A SOT−553 SOT−953 UDFN6 −20 ±20 −20 −20 ±25 ±50 −65 to +150 260 +150 377 320 324 254 154 mA mA mA mA mA °C °C °C °C/W PD Power Dissipation in Still Air SC−88A 332 mW SC−74A 390 SOT−553 386 SOT−953 491 UDFN6 812 MSL Moisture Sensitivity Level 1 − FR VESD Flammability Rating ESD Withstand Voltage (Note 3) Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in − Human Body Model 2000 V Charged Device Model 1000 ILatchup Latchup Performance (Note 4) $100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Applicable to devices with outputs that may be tri−stated. 2. Measured with minimum pad spacing on an FR4 board, using 10mm−by−1inch, 2 ounce copper trace no air flow per JESD51−7. 3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.


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