MPC993

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dynamic Switch PLL Clock Driver The MPC993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. MPC993 Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control/Statis I/O 3.3V Operation 32–Lead TQFP Packaging ±50ps Cycle–Cycle Jitter FA SUFFIX 32–LEAD PLASTIC TQFP PACKAGE CASE 751D–04 The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will automatically switch from the bad reference clock input to the good one. During this dynamic switch of the input references, the MPC993 outputs will slew, with minimal period disturbances to the new phase. Alarm_Reset Man_OVerride Dynamic Switch Logic Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR PLL_En ÷2 PLL ÷4 Inp0bad Inp1bad Clk_Selected Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Figure 1. Block Diagram 9/97 © Motorola, Inc. 1997 1 REV 0 MPC993 VCC 24 Qa1 Qa1 Qa0 Qa0 VCC VCCA Man_...