Document
E2O0020-27-X3
¡ Semiconductor MSM82C55A-2RS/GS/VJS
¡ Semiconductor CMOS PROGRAMMABLE PERIPHERAL INTERFACE
www.DataSheet4U.com This version: Jan. 1998 MSM82C55A-2RS/GS/VJS Previous version: Aug. 1996
GENERAL DESCRIPTION
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU. This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are TTL interface compatible.
FEATURES
• High speed and low power consumption due to 3m silicon gate CMOS technology • 3 V to 6 V single power supply • Full static operation • Programmable 24-bit I/O ports • Bidirectional bus operation (Port A) • Bit set/reset function (Port C) • TTL compatible • Compatible with 8255A-5 • 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS) • 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS) • 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)
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CIRCUIT CONFIGURATION
8 VCC 8 GND 8 Group A Control 4 Group A Port C (High Order 4 Bits) 4 PC4 - PC7 Group A Port A (8) 8 PA0 - PA7
8 D 0 - D7
Data Bus Buffer
8
Internal Bus Line
4
8 RD WR RESET CS A0 A1 Read/ Write Control Logic Group B Control 8
Group B Port C (Low Order 4 Bits)
4 PC0 - PC3
Group B Port B (8)
8 PB0 - PB7
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PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
1 2 3 4 RD 5 CS 6 GND 7 A1 8 A0 9 PC7 10 PC6 11 PC5 12 PC4 13 PC0 14 PC1 15 PC2 16 PC3 17 PB0 18 PB1 19 PB2 20 PA3 PA2 PA1 PA0 33 32 31 30 29 28 27 26 25 24 23
NC 12 PC3 13 PB0 14 PB1 15 PB2 16 17 PB3 18 PB4 19 PB5 20 PB6 21 NC 22 VCC
44 pin Plastic QFP
44 RD 43 PA0 42 PA1 41 PA2 40 PA3 38 PA4 37 PA5 36 PA6 35 PA7 34 WR 39 VCC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3
CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2
1 2 3 4 5 6 7 8 9 10 11
RESET D0 D1 D2. D3 D4 D5 D6 D7 VCC PB7
6 RD 5 PA0
44 pin Plastic QFJ
4 PA1 3 PA2 2 PA3 44 PA4 43 PA5 42 PA6 41 PA7 40 WR 1 NC
CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1
7 8 9 10 11 12 13 14 15 16 17
PB0 20 PB1 21 PB2 22 NC 23 PB3 24 PB4 25 PB5 26 PB6 27 PC2 18 PC3 19 PB7 28
39 38 37 36 35 34 33 32 31 30 29
RESET D0 D1 D2. D3 NC D4 D5 D6 D7 VCC
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Symbol VCC VIN VOUT TSTG PD Conditions Ta = 25°C with respect to GND — Ta = 25°C 1.0 Rating
MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS
Unit V V V °C 1.0 W
–0.5 to +7 –0.5 to VCC +0.5 –0.5 to VCC +0.5 –55 to +150 0.7
OPERATING RANGE
Parameter Supply Voltage Operating Temperature Symbol VCC Top Range 3 to 6 –40 to 85 Unit V °C
RECOMMENDED OPERATING RANGE
Parameter Supply Voltage Operating Temperature "L" Input Voltage "H" Input Voltage Symbol VCC Top VIL VIH Min. 4.5 –40 –0.3 2.2 Typ. 5 +25 — — Max. 5.5 +85 +0.8 VCC + 0.3 Unit V °C V V
DC CHARACTERISTICS
MSM82C55A-2 Min. — 4.2 3.7 VCC = 4.5 V to 5.5 V Ta = –40°C to +85°C (CL = 0 pF) –1 –10 — Typ. — — — — — 0.1 Max. 0.4 — — 1 10 10
Parameter "L" Output Voltage "H" Output Voltage Input Leak Current Output Leak Current Supply Current (Standby) Average Supply Current (Active)
Symbol VOL VOH ILI ILO ICCS
Conditions IOL = 2.5 mA IOH = –40 mA IOH = –2.5 mA 0 £ VIN £ VCC 0 £ VOUT £ VCC CS ≥ VCC –0.2 V VIH ≥ VCC –0.2 V VIL £ 0.2 V I/O Wire Cycle 82C55A-2 ...8 MHzCPU Timing
Unit V V V mA mA mA
ICC
—
—
8
mA
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AC CHARACTERISTICS
Parameter Setup Time of Address to the Falling Edge of RD Hold Time of Address to the Rising Edge of RD RD Pulse Width Delay Time from the Falling Edge of RD to the Output of Defined Data Delay Time from the Rising Edge of RD to the Floating of Data Bus Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR Setup Time of Address before the Falling Edge of WR Hold Time of Address after the Rising Edge of WR WR Pulse Width Setup Time of Bus Data before the Rising Edge of WR Hold Time of Bus Data after the Rising Edge of WR Delay Time from the rising Edge of WR to the Output of Defined Data Setup Time of Port Data before the Falling Edge of RD Hold Time of Port Data after the Rising Edge of RD ACK Pulse Width STB Pulse Width Setup Time of Port Data before the rising Edge of STB Hold Time of Port Bus Data after the rising Edge of STB Delay Time from the Falling Edge of ACK to the Output of Defined Data Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) Delay Time from the Rising Edge of WR to the Falling Edge of OBF Delay Time from the Falling Edge of ACK to the Rising E.