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TSA5060A Dataheets PDF



Part Number TSA5060A
Manufacturers NXP
Logo NXP
Description 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer
Datasheet TSA5060A DatasheetTSA5060A Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET TSA5060A 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer Product specification Supersedes data of 2000 Sep 19 File under Integrated Circuits, IC02 2000 Oct 24 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer FEATURES • Complete 1.3 GHz single chip system • Optimized for low phase noise • Selectable divide-by-two prescaler • Operation up to 1.3 GHz without divide-by-two prescaler • Sele.

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INTEGRATED CIRCUITS DATA SHEET TSA5060A 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer Product specification Supersedes data of 2000 Sep 19 File under Integrated Circuits, IC02 2000 Oct 24 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer FEATURES • Complete 1.3 GHz single chip system • Optimized for low phase noise • Selectable divide-by-two prescaler • Operation up to 1.3 GHz without divide-by-two prescaler • Selectable reference divider ratio • Compatible with UK-DTT (Digital Terrestrial Television) offset requirements • Selectable crystal or comparison frequency output • Four selectable charge pump currents • Four selectable I2C-bus addresses • Standard and fast mode I2C-bus • I2C-bus compatible with 3.3 and 5 V microcontrollers • 5-level Analog-to-Digital Converter (ADC) • Low power consumption • Three I/O ports and one output port. APPLICATIONS • Digital terrestrial and cable tuning systems • Hybrid (digital and analog) terrestrial and cable tuning systems • Digital set-top boxes. GENERAL DESCRIPTION The TSA5060A is a single chip PLL frequency synthesizer designed for terrestrial and cable tuning systems up to 1.3 GHz. The RF preamplifier drives the 17-bit main divider enabling a step size equal to the comparison frequency, for an input frequency up to 1.3 GHz covering the complete terrestrial frequency range. A fixed divide-by-two additional prescaler can be inserted between the preamplifier and the main divider. In this case, the step size is twice the comparison frequency. TSA5060A The comparison frequency is obtained from an on-chip crystal oscillator that can also be driven from an external source. Either the crystal frequency or the comparison frequency can be switched to the XT/COMP output pin to drive the reference input of another synthesizer or the clock input of a digital demodulation IC. Both divided and comparison frequencies are compared in the fast phase detector which drives the charge pump. The loop amplifier is also on-chip, however an external NPN transistor to drive directly the 33 V tuning voltage. Control data is entered via the I2C-bus; five serial bytes are required to address the device, select the main divider ratio, the reference divider ratio, program the four output ports, set the charge pump current, select the prescaler by two, select the signal to switch to the XT/COMP output pin and select a specific test mode. Three of the four output ports can also be used as input ports and a 5-level ADC is provided. Digital information concerning the input ports and the ADC can be read out of the TSA5060A on the SDA line (one status byte) during a READ operation. A flag is set when the loop is ‘in-lock’ and is read during a READ operation, as well as the Power-on reset flag. The device has four programmable addresses, programmed by applying a specific voltage at pin AS, enabling the use of multiple synthesizers in the same system. 2000 Oct 24 2 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer QUICK REFERENCE DATA VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; unless otherwise specified. SYMBOL VCC ICC fi(RF) Vi(RF)(rms) PARAMETER supply voltage supply current RF input frequency RF input voltage (RMS value) fi(RF) from 64 to 150 MHz; note 1 Tamb = 25 °C CONDITIONS MIN. 4.5 30 64 12.6 −25 fi(RF) from 150 to 1300 MHz; note 1 7.1 −30 fxtal Tamb Tstg Note 1. Asymmetrical drive on pin RFA or RFB; see Fig.3. ORDERING INFORMATION TYPE NUMBER TSA5060AT TSA5060ATS PACKAGE NAME SO16 SSOP16 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm crystal frequency ambient temperature storage temperature 4 −20 −40 TSA5060A TYP. 5.0 37 − − − − − − − − MAX. 5.5 45 1300 300 +2.5 300 +2.5 16 +85 +150 UNIT V mA MHz mV dBm mV dBm MHz °C °C VERSION SOT109-1 SOT369-1 2000 Oct 24 3 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer BLOCK DIAGRAM TSA5060A handbook, full pagewidth 3 XTAL 2 XTAL OSCILLATOR REFERENCE DIVIDER XT/COMP LOCK DETECT 4-BIT LATCH DIGITAL PHASE COMPARATOR RFA RFB 13 14 PRE AMP DIVIDER 1/2 17-BIT DIVIDER CHARGE PUMP 1-BIT LATCH 17-BIT LATCH DIVIDE RATIO 1 2-BIT LATCH AMP AS SCL SDA 4 6 5 I2C-BUS TRANSCEIVER 12 15 ADC 11 3-BIT ADC POWER-ON RESET 7 8 9 10 FCE717 CP 16 DRIVE VCC GND 3-BIT INPUT PORTS 4-BIT LATCH AND OUTPUT PORTS MODE CONTROL LOGIC TSA5060A P3 P2 P1 P0 Fig.1 Block diagram. 2000 Oct 24 4 Philips Semiconductors Product specification 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer PINNING SYMBOL CP XTAL XT/COMP AS SDA SCL P3 P2 P1 P0 ADC VCC RFA RFB GND DRIVE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION charge pump output crystal oscillator input fxtal or fcomp signal output I2C-bus address selection input I2C-bus serial data input/output I2C.


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