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MT90880 Dataheets PDF



Part Number MT90880
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description (MT90880 - MT90883) TDM to Packet Processors
Datasheet MT90880 DatasheetMT90880 Datasheet (PDF)

MT90880/1/2/3 TDM to Packet Processors Data Sheet Features • • • • • • • • WAN interface, consisting of 32 input and output streams at 2.048 or 8.192 Mbs Up to 1024 bi-directional 64 Kbs channels N * 64 Kbs trunking of channels across any stream and channel 1 K by 1 K non-blocking TDM switch Local TDM interface, with 32 streams at 2.048, 4.096 and 8.192 Mbs Flexible, multi-protocol packet encapsulation Dual 100 Mbs MII interfaces for redundancy or for load balancing Quality of service features, .

  MT90880   MT90880


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MT90880/1/2/3 TDM to Packet Processors Data Sheet Features • • • • • • • • WAN interface, consisting of 32 input and output streams at 2.048 or 8.192 Mbs Up to 1024 bi-directional 64 Kbs channels N * 64 Kbs trunking of channels across any stream and channel 1 K by 1 K non-blocking TDM switch Local TDM interface, with 32 streams at 2.048, 4.096 and 8.192 Mbs Flexible, multi-protocol packet encapsulation Dual 100 Mbs MII interfaces for redundancy or for load balancing Quality of service features, including weighted fair queuing, strict priority and queue size limit thresholds High performance 33 MHz / 66 MHz 32 bit PCI bus Integral Stratum 4E PLL for synchronisation to the TDM domain Power consumption of less than 0.75 W Ordering Information MT90880B/IG/BP1N MT90881A/IG/BP1N MT90882B/IG/BP1N MT90883A/IG/BP1N 456 ball PBGA 456 ball PBGA 456 ball PBGA 456 ball PBGA December 2004 -40°C to +85 °C Applications • • • • • Packet backplane interconnection Circuit Emulation over packet domain Internet Off-load Remote Access Concentrators H.100/H.110 extension and expansion • • • Host Control/Data Interface 32 bit, 33MHz / 66MHz 32 PCI WAN Access Interface 32 ST-Bus TDM ports (1024 bi-directional channels) Administration PCI Interface Packet Switch Fabric Interface Dual Redundant 100 Mbit/s MII Interfaces 1Kx1K TDM Switch Packetizing and Circuit Emulation Dual Packet Interface MAC TDM ReFormatter Memory Manager Local TDM Interface Packet Memory e.g. for connection to local resource pool 0.125 - 8 MBytes SSRAM Figure 1 - MT90880 High Level Overview 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT90880/1/2/3 Description Data Sheet The MT9088x is a family of highly functional TDM to Packet bridging devices. It provides a bridge between a WAN environment based on constant bit rate TDM streams and a packet domain based on Ethernet technology. It is capable of assembling user-defined packets of TDM traffic from the WAN Access Interface and transmitting them from the Ethernet interfaces using a variety of protocols. If external processing is required (e.g., HDLC or modem termination) the traffic can be switched to a local interface using the internal TDM switch. Packets received from the Ethernet interfaces are parsed to determine the egress destination, and are appropriately queued either to the WAN Access Interface or to the PCI interface. An integrated DMA controller is used to transfer packets to and from the PCI interface with a minimum of CPU intervention. Variants There are four device variants in the MT9088x family: • • • • MT908801024 bi-directional channels, integral TDM switch MT908811024 bi-directional channels, no TDM switch MT90882256 bi-directional channels, integral TDM switch MT90883256 bi-directional channels, no TDM switch Feature No. of WAN streams Local Port No. of Available Channels TDM Switch Availability PCI Interface MII Interface RMII Interface JTAG MT90880 32 Yes 1024 Master mode only 33 / 66 MHz Yes Yes Yes MT90881 32 No 1024 Not Available 33 / 66 MHz Yes Yes Yes MT90882 8 Yes 256 Master mode only 33 / 66 MHz Yes Yes Yes MT90883 8 No 256 Not Available 33 / 66 MHz Yes Yes Yes Table 1 - Variant Options Related Documents This data sheet should be read in conjunction with the following related documents and application notes: Title 1. MT9088x Programmers Model 2. MT9088x API User Guide 3. MSAN-198 - Performing Clock Recovery for Circuit Emulation when using the MT90880 4. MSAN-199 - Unstructured Circuit Emulation Using the MT90880 5. MSAN-200 - MT90880 TDM Replacement Packet Backplane Author Zarlink Zarlink Zarlink Zarlink Zarlink Document Number DM5708 DM5805 AN5789 AN5790 AN5791 Issue / Date 1.0, Aug. 2002 1.0, Sept. 2002 1, Aug. 2002 1, Aug. 2002 1, Aug. 2002 Table 2 - Related Documents 2 Zarlink Semiconductor Inc. MT90880/1/2/3 The following external documents and standards are referenced in this data sheet: Title 1. Local and Metropolitan Area Networks, Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications 2. PCI Local Bus Specification 3. RMII TM Specification Data Sheet Author IEEE Document Number IEEE 802.3u Issue / Date 1995 4. Test Access Port and Boundary Scan Architecture 5. Circuit Emulation Service Interoperability Specification 6. Specifications of (DBCES) Dynamic Bandwidth Utilization - in 64 KBPS Time Slot Trunking over ATM - Using CES 7. ST-BUS Generic Device Specification 8. H.110 Hardware Compatibility Specification: CT Bus 9. H-MVIP Standard 10. Clocks for the Synchronized Network: Common Generic Criteria PCI SIG RMII consortium IEEE ATM Forum ATM Forum 2.2 Rev 1.2, March 1998 IEEE 1149.1 af-vtoa-0078 af-vtoa-0085 1990 Ver 2.0, Jan. 1997 July 1997 Mitel ECTF GO-MVIP Telcordia ITU-T ITU-T MSAN-126 11. The Control of Jitter and Wander within d.


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