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MT9041B Dataheets PDF



Part Number MT9041B
Manufacturers Mitel Networks Corporation
Logo Mitel Networks Corporation
Description T1/E1 System Synchronizer
Datasheet MT9041B DatasheetMT9041B Datasheet (PDF)

MT9041B T1/E1 System Synchronizer Advance Information Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C3, C4, C8 and C16 output clock signals Provides 3 different styles of 8 KHz framing pulses Attenuates wander from 1.9 Hz DS5059 ISSUE 3 Septemner 1999 Ordering Informat.

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MT9041B T1/E1 System Synchronizer Advance Information Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C3, C4, C8 and C16 output clock signals Provides 3 different styles of 8 KHz framing pulses Attenuates wander from 1.9 Hz DS5059 ISSUE 3 Septemner 1999 Ordering Information MT9041BP 28 Pin PLCC -40 to +85 °C • • • • • Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications. Applications • • Synchronization and timing control for multitrunk T1 and E1 systems ST-BUS clock and frame pulse sources VDD VSS OSCi OSCo C1.5o REF Phase Detector Loop Filter DCO Output Interface Circuit C3o C2o C4o C8o C16o F0o F8o F16o Mode Select Divider MS RST FS1 FS2 Figure 1 - Functional Block Diagram 1 MT9041B IC0 VSS RST FS1 FS2 REF NC Advance Information 4 3 2 1 28 27 26 25 24 23 22 21 20 19 VDD OSCo OSCi F16o F0o F8o C1.5o 5 6 7 8 9 10 11 MT9041B IC0 IC0 MS IC0 IC0 IC1 IC0 12 13 14 15 16 17 18 Figure 2 - Pin Connections Pin Description Pin # 1 2 3 4 5 6 Name VSS IC0 NC REF VDD OSCo Ground. 0 Volts. Internal Connect. Connect to Vss No Connect. Connect to Vss Reference (TTL Input). PLL reference clock. Positive Supply Voltage. +5VDC nominal. Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi, see Figure 6. For clock oscillator operation, this pin is left unconnected, see Figure 5. Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is connected to a clock source, see Figure 5. Frame Pulse ST-BUS 16.384Mb/s (CMO7S Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 16.384Mb/s. See Figure 11. Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 11. Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS operation at 8.192Mb/s. See Figure 11. Clock 1.544MHz (CMOS Output). This output is used in T1 applications. Clock 3.088MHz (CMOS Output). This optional output is used in T1 applications. Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. Ground. 0 Volts. Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/ s. Positive Supply Voltage. +5VDC nominal. Description 7 OSCi 8 F16o 9 F0o 10 F8o 11 12 13 14 15 16 17 18 2 C1.5o C3o C2o C4o VSS C8o C16o VDD C3o C2o C4o VSS C8o C16o VDD Advance Information Pin Description (continued) Pin # 19 20 21 22 23 Name IC0 IC1 IC0 IC0 MS Internal Connect. Connect to Vss Internal Connect. Leave open Circuit Internal Connect. Connect to Vss Internal Connect. Connect to Vss Description MT9041B Mode/Control Select (TTL Input). This pin, determines the device’s state (Normal, or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3. Internal Connect. Connect to Vss Internal Connect. Connect to Vss Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See Table 1. Frequency Select 1 (TTL Input). See pin description for FS2. Reset (Schmitt Input). A logic low at this input resets the MT9041B. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs are at logic high. Following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in Figure 10. FS2 0 0 1 1 FS1 0 1 0 1 Input Frequency Reserved 8kHz 1.544MHz 2.048MHz 24 25 26 IC0 IC0 FS2 .


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