MT9040

MT9040 T1/E1 Synchronizer Data Sheet Features Supports AT&T TR62411 and Bellcore GR-1244CORE and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 different styles of 8 KHz framing pulses Attenuates wander from 1.9Hz Fast lock mode JTAG Boundary Scan The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9040 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy and capture range for these specifications. Ordering Information MT9040AN 48 pin SSOP -40° C to +85° C November 2003 Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Applications Synchronization and timing control for multitrunk T1 and E1 systems ST-BUS clock and frame pulse source OSCi OSCo FLOCK LOCK VDD VSS Master Clock TCK TDI TMS TRST TDO IEEE 1149.1a DPLL Output Interface Circuit Input Impairment Monitor REF C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP Control State Machine...