MC74HC75

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 2-Bit Transparent Latch High–Performance Silicon–Gate CMOS The MC74HC75 is identical in pinout to the LS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 2–bit transparent latches. Each latch stores the input data while Latch Enable is at a logic low. The outputs follow the data inputs when Latch Enable is at a logic high. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 80 FETs or 20 Equivalent Gates 16 1 MC74HC75 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING INFORMATION MC74HCXXN MC74HCXXD Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAM Q0a D0a DATA INPUTS D0 D1 2, 6 3, 7 2–BIT TRANSPARENT LATCH 16, 10 1, 11 15, 9 14, 8 Q0 Q0 Q1 Q1 D1a LEb VCC D0b D1b Q1b LATCH ENABLE 13, 4 PIN 5 = VCC PIN 12 = GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q0a Q1a Q1a LEa GND Q0b Q0b Q1b FUNCTION TABLE Inputs D L H X Latch Enable H H L Outputs Q L H Q0 Q H L Q0 X = don’t care Q0 = latched data 10/95 © Motorola, Inc. 1995 1 REV 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ...