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DATA SHEET www.onsemi.com
Dual D Flip-Flop with Set and Reset
MC74HC74A, MC74HCT74A
The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip−flop. The Set and Reset inputs are asynchronous.
Features
• Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range:
2.0 to 6.0 V (HC), 4.5 to 5.5 V (HCT)
• Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the JEDEC Standard No. 7.0 A Requirements • Chip Complexity: 136 FETs or 34 Equivalent Gates • −Q Suffix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14 1
MARKING DIAGRAMS
14
SOIC−14 D SUFFIX CASE 751A
1
XXXXXXXXX AWLYWW
14 1
TSSOP−14 DT SUFFIX CASE 948G
14
XXXX XXXX ALYWG
G 1
XXXX A WL, L Y WW, W G or G
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
February, 2024 − Rev. 15
Publication Order Number: MC74HC74A/D
MC74HC74A, MC74HCT74A
RESET 1 1
DATA 1 2 3
CLOCK 1 SET 1 4 13
RESET 2
DATA 2 12 11
CLOCK 2 10
SET 2
5 Q1
6 Q1
PIN 14 = VCC PIN 7 = GND
9 Q2
8 Q2
Figure 1. Logic Diagram
RESET 1 1 DATA 1 2
CLOCK 1 3 SET 1 4 Q1 5 Q1 6 GND 7
14 VCC 13 RESET 2 12 DATA 2 11 CLOCK 2 10 SET 2
9 Q2 8 Q2
Figure 2. Pinout (Top View)
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q Q
LH HL LL HH HH HH HH HH
XX
HL
XX
LH
X X H* H*
H HL
L
LH
L X No Change
H X No Change
X No Change
*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
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MC74HC74A, MC74HCT74A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC VIN VOUT IIN IOUT ICC IIK IOK TSTG TL TJ qJA
DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current, per Pin DC Output Diode Current, per Pin DC Supply Current, VCC and GND Pins Input Clamp Current (VIN < 0 or VIN > VCC) Output Clamp Current (VOUT < 0 or VOUT > VCC) Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1)
SOIC−14 TSSOP−14
–0.5 to +6.5 –0.5 to VCC + 0.5 –0.5 to VCC + 0.5
±20 ±25 ±50 ±20 ±20 –65 to +150 260 ±150 116 150
V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 25_C
SOIC−14
1077
mW
TSSOP−14
833
MSL Moisture Sensitivity
Level 1
−
FR
Flammability Rating
Oxygen Index: 28 to 34 UL 94 V−0 @
−
0.125 in
VESD ESD Withstand Voltage (Note 2)
Human Body Model
> 2000
V
Charged Device Model
N/A
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 76mm−by−114mm, 2−ounce copper trace no air flow per JESD51−7. 2. HBM tested to EIA / JESD22−A114−A. CDM tested to JESD22−C101−A. JEDEC recommends that ESD qualification to EIA/JESD22−A115A
(Machine Model) be discontinued.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
MC74HC
VCC VIN, VOUT
TA tr, tf
DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) (Note 3) Operating Free−Air Temperature Input Rise and Fall Time
MC74HCT
2.0
6.0
V
0
VCC
V
–55
+125
_C
VCC = 2.0 V
0
VCC = 4.5 V
0
VCC = 6.0 V
0
1000
ns
500
400
VCC DC Supply Voltage (Referenced to GND)
4.5
5.5
V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) (Note 3)
0
VCC
V
TA
Operating Free−Air Temperature
–55
+125
_C
tr, tf
Input Rise and Fall Time
0
500
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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MC74HC74A, MC74HCT74A
DC ELECTRICAL CHARACTERISTICS (MC74HC74A)
Symbol VIH
Parameter Minimum High−Level Input Voltage
Test Conditions
VOUT .