Document
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564441, 4564841, 4564163
64M-bit Synchronous DRAM 4-bank, LVTTL
Description
The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock.
www.DataSheet4U.com The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by A12 and A13 (Bank Select) • Byte control (×16) by LDQM and UDQM • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4, 8 and full page) • Programmable /CAS latency (2 and 3) • Automatic precharge and controlled precharge • CBR (auto) refresh and self refresh • ×4, ×8, ×16 organization • Single 3.3 V ± 0.3 V power supply • LVTTL compatible inputs and outputs • 4,096 refresh cycles / 64 ms • Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0149N10 (Ver.1.0) (Previous No. M12621EJCV0DS00) Date Published August 2001 (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µPD4564441, 4564841, 4564163
Ordering Information
Part number Organization (word × bit × bank) 4M × 4 × 4 Clock frequency MHz (MAX.) 125 100 100 2M × 8 × 4 125 100 100 1M × 16 × 4 125 100 100 Package 54-pin Plastic TSOP (II) (10.16mm (400))
µPD4564441G5-A80-9JF µPD4564441G5-A10-9JF µPD4564441G5-A10B-9JF µPD4564841G5-A80-9JF µPD4564841G5-A10-9JF µPD4564841G5-A10B-9JF µPD4564163G5-A80-9JF µPD4564163G5-A10-9JF µPD4564163G5-A10B-9JF
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Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Part Number
[ x4, x8 ]
µPD4564841G5 - A80
NEC Memory Synchronous DRAM Memory density 64 : 64M bits Minimum cycle time 80 : 8 ns (125 MHz) 10 : 10 ns (100 MHz) 10B : 10 ns (100 MHz)
www.DataSheet4U.com Organization
4 : x4 8 : x8
Number of banks 4 : 4 banks
Interface 1 : LVTTL
Low voltage A : 3.3 ± 0.3 V
Package
[ x16 ]
Organization 16 : x16 Number of banks and Interface 3 : 4 banks, LVTTL
163
G5 : TSOP (II)
Data Sheet E0149N10
3
µPD4564441, 4564841, 4564163
Pin Configurations
/xxx indicates active low signal. [µPD4564441] 54-pin Plastic TSOP (II) (10.16mm (400)) 4M words × 4 bits × 4 banks
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VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss NC VssQ NC DQ3 VccQ NC NC VssQ NC DQ2 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
A0 to A13 CLK CKE /CS /RAS /CAS /WE DQM VCC VSS VCCQ VSSQ NC
Note
: Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A11 : Row address inputs A0 to A9 : Column address inputs A12, A13 : Bank select
DQ0 to DQ3 : Data inputs / outputs
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Data Sheet E0149N10
µPD4564441, 4564841, 4564163
[µPD4564841] 54-pin Plastic TSOP (II) (10.16mm (400)) 2M words × 8 bits × 4 banks
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VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ7 VssQ NC DQ6 VccQ NC DQ5 VssQ NC DQ4 VccQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
A0 to A13 CLK CKE /CS /RAS /CAS /WE DQM VCC VSS VCCQ VSSQ NC
Note
: Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A11 : Row address inputs A0 to A8 : Column address inputs A12, A13 : Bank select
DQ0 to DQ7 : Data inputs / outputs
Data Sheet E0149N10
5
µPD4564441, 4564841, 4564163
[µPD4564163] 54-pin Plastic TSOP (II) (10.16mm (400)) 1M words × 16 bits × 4 banks
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VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM /WE /CAS /RAS /CS A13 A12 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 .