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ST25C01 Dataheets PDF



Part Number ST25C01
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description (ST2xxx) SERIAL 1K 128 x 8 EEPROM
Datasheet ST25C01 DatasheetST25C01 Datasheet (PDF)

ST24/25C01, ST24C01R ST24/25W01 SERIAL 1K (128 x 8) EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: – 3V to 5.5V for ST24x01 versions – 2.5V to 5.5V for ST25x01 versions – 1.8V to 5.5V for ST24C01R version only HARDWARE WRITE CONTROL VERSIONS: ST24W01 and ST25W01 TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4 BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRA.

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ST24/25C01, ST24C01R ST24/25W01 SERIAL 1K (128 x 8) EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: – 3V to 5.5V for ST24x01 versions – 2.5V to 5.5V for ST25x01 versions – 1.8V to 5.5V for ST24C01R version only HARDWARE WRITE CONTROL VERSIONS: ST24W01 and ST25W01 TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4 BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES ST24C/W01 are replaced by the M24C01 ST25C/W01 are replaced by the M24C01-W ST24C01R is replaced by the M24C01-R DESCRIPTION This specification covers a range of 1K bits I2C bus EEPROM products, t he ST24/25C01, the ST24C01R and the ST24/25W01. In the text, products are referred to as ST24/25x01, where "x" is: "C" for Standard version and "W" for hardware Write Control version. Table 1. Signal Names E0-E2 SDA SCL MODE WC VCC VSS Chip Enable Inputs Serial Data Address Input/Output Serial Clock Multibyte/Page Write Mode (C version) Write Control (W version) Supply Voltage Ground 8 1 PSDIP8 (B) 0.25mm Frame 8 1 SO8 (M) 150mil Width Figure 1. Logic Diagram VCC 3 E0-E2 SCL MODE/WC* ST24x01 ST25x01 ST24C01R SDA VSS AI00839D Note: WC signal is only available for ST24/25W01 products. November 1997 This is information on a product still in production but not recommended for new design 1/16 ST24/25C01, ST24C01R, ST24/25W01 Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST24x01 ST25x01 ST24C01R E0 E1 E2 VSS 1 2 3 4 8 7 6 5 AI00840D ST24x01 ST25x01 ST24C01R VCC MODE/WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5 AI00841E VCC MODE/WC SCL SDA Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) Value –40 to 125 –65 to 150 Unit °C °C °C V V V V (SO8 package) (PSDIP8 package) 40 sec 10 sec 215 260 –0.6 to 6.5 –0.3 to 6.5 4000 500 Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω). DESCRIPTION (cont’d) The ST24/25x01 are 1K bit electrically erasable programmable memories (EEPROM), organized as 128 x 8 bits. They are manufactured in SGSTHOMSON’s Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The memories operate with a power supply value as low as 1.8V for the ST24C01R only. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. The memories are compatible with the I 2C standard, two wire serial interface which uses a bi-direc- tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This is used together with 3 chip enable inputs (E2, E1, E0) so that up to 8 x 1K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit. 2/16 ST24/25C01, ST24C01R, ST24/25W01 Table 3. Device Select Code Device Code Bit Device Select Note: The MSB b7 is sent first. Chip Enable b4 0 b3 E2 b2 E1 b1 E0 RW b0 RW b7 1 b6 0 b5 1 Table 4. Operating Modes (1) Mode Current Address Read Random Address Read Sequential Read Byte Write Multibyte Write Page Write (2) RW bit ’1’ ’0’ ’1’ ’1’ ’0’ ’0’ ’0’ MODE X X X X VIH VIL Bytes 1 1 1 to 128 1 4 8 Initial Sequence START, Device Select, RW = ’1’ START, Device Select, RW = ’0’, Address, reSTART, Device Select, RW = ’1’ Similar to Current or Random Mode START, Device Select, RW = ’0’ START, Device Select, RW = ’0’ START, Device Select, RW = ’0’ Notes: 1. X = VIH or VIL 2. Multibyte Write not available in ST24/25W01 versions. When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same.


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