CY7C402

1CY 7C40 2 CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO) Processed with high-speed CMOS for optimum speed/power 25-MHz data rates 50-ns bubble-through time—25 MHz Expandable in word width and/or length 5-volt power supply ± 10% tolerance, both commercial and military Independent asynchronous inputs and outputs TTL-compatible interface Output enable function available on CY7C403 and CY7C404 Capable of withstanding greater than 2001V electrostatic discharge Pin compatible with MMI 67401A/67402A words. Both the CY7C403 and CY7C404 have an output enable (OE) function. The devices accept 4- or 5-bit words at the data input (DI0 – DIn) under the control of the shift in (SI) input. The stored words stack up at the output (DO0 – DOn) in the order they were entered. A read command on the shift out (SO) input causes the next to last word to move to the output and all data shifts down once in the stack. The input ready (IR) signal acts as a flag to indicate when the input is ready to accept new data (HIGH), to indicate when the FIFO is full (LOW), and to provide a signal for a cascading. The output ready (OR) signal is a flag to indicate the output contains valid data (HIGH), to indicate the FIFO is empty (LOW), and to provide a signal for cascading. Parallel expansion for wider words is accomplished by logically ANDing th...