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STW20NA50

ST Microelectronics

N-CHANNEL Power MOSFET

STW20NA50 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR TYPE STW20NA50 s s s s s s s V DSS 500 V R DS( on) < ...


ST Microelectronics

STW20NA50

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STW20NA50 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR TYPE STW20NA50 s s s s s s s V DSS 500 V R DS( on) < 0.27 Ω ID 20 A TYPICAL RDS(on) = 0.22 Ω ± 30V GATE TO SOURCE VOLTAGE RATING 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW INTRINSIC CAPACITANCES GATE GHARGE MINIMIZED REDUCED THRESHOLD VOLTAGE SPREAD TO-247 3 2 1 DESCRIPTION This series of POWER MOSFETS represents the most advanced high voltage technology. The optimized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior switching performance. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VD S V DG R V GS ID ID ID M( ) P tot T stg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 kΩ ) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 oC Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating Factor Storage Temperature Max. Operating Junction Temperature o o Value 500 500 ± 30 20 12.7 80 250 2 -65 to 150 150 Unit V V V A A A W W/o C o o C C () Pulse width limited by safe operating area December 1996 1/9 STW20NA50 THERMAL DATA R thj-cas e Rthj- amb Rthj- amb Tl Thermal Resistance Junction-case Thermal Resistance Ju...




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