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DS1640 Dataheets PDF



Part Number DS1640
Manufacturers Dallas Semiconducotr
Logo Dallas Semiconducotr
Description Personal Computer Power FET
Datasheet DS1640 DatasheetDS1640 Datasheet (PDF)

DS1640/DS1640C Personal Computer Power FET www.dalsemi.com FEATURES Contains four P channel power FET switches that can each supply over 300 mA @ 0.2 volts drop Controlled directly from CMOS or TTL level signals Fast switching time of less than 10 µs at rated supply current 16-pin DIP or 16-pin SOIC surface mount package Positive logic signal turns each FET on and ground or low level signal turns each FET off Off condition allows less than 50 nA of current flow Low control gate capacitance of l.

  DS1640   DS1640



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DS1640/DS1640C Personal Computer Power FET www.dalsemi.com FEATURES Contains four P channel power FET switches that can each supply over 300 mA @ 0.2 volts drop Controlled directly from CMOS or TTL level signals Fast switching time of less than 10 µs at rated supply current 16-pin DIP or 16-pin SOIC surface mount package Positive logic signal turns each FET on and ground or low level signal turns each FET off Off condition allows less than 50 nA of current flow Low control gate capacitance of less than 5 pF FET gates can either follow inputs or be latched Designed for use with power supplies ranging from +3 to +5 volts PIN ASSIGNMENT IN1 GATE1 OUT1 LATCH GND OUT2 GATE2 IN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN4 GATE4 OUT4 NC VCC OUT3 GATE3 IN3 16-Pin DIP (300-mil) See Mech. Drawings Section IN1 GATE1 OUT1 LATCH GND OUT2 GATE2 IN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN4 GATE4 OUT4 NC VCC OUT3 GATE3 IN3 16-Pin DIP SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION VCC GND IN1-IN4 OUT1-OUT4 GATE1-GATE4 NC LATCH - +3 to +5 Volt Input - Ground - FET Sources - FET Drains - FET Control Gates - No Connection - Gate Inputs Latch Control DESCRIPTION The DS1640 contains four P channel power MOS FETs designed as switches to conserve power in personal computer systems. When connected to power management control units, power consuming devices like disk drives or display panel backlights can be routinely shut down to conserve battery or main power supply energy. The P channel power MOS FETs are individually controlled and are capable of handling 300 mA each continuously with less than 0.2 volts drop from input to output. The device requires a +3 Û +5 volt power supply input which is used to power internal logic and to operate a gate bias generator. 1 of 4 111999 DS1640/DS1640C OPERATION With +3 Û +5 volts applied between the VCC pin and ground, any one of four inputs can be connected or disconnected from its respective output based on the bias applied to the control gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the control gates, enabling the switches to be switched both independently and asynchronously. With a transition from logic 0 to logic 1 on the latch pin, the input levels present on the gate inputs are locked by the four internal latches, maintaining the corresponding FET gates at those levels. As long as the latch input is maintained at logic 1, the FET gate levels are maintained. When the latch input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates without being latched. A TTL or CMOS logic 1 turns a switch completely on and TTL or CMOS logic 0 turns a switch completely off. The four switches can be operated independently or two or more can be connected in para.


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