UPD485505

DATA SHEET MOS INTEGRATED CIRCUIT µPD485505 LINE BUFFER 5K-WORD BY 8-BIT Description The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied to the version P and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping). Features 5,048 words by 8 bits Asynchronous read/write operations available Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns) 15 to 5,048 bits (Cycle time: 35 ns) Power supply voltage VCC = 5.0 V ± 0.5 V Suitable for sampling one line of A3 size paper (16 dots/mm) All input/output TTL compatible 3-state output Full static operation; data hold time = infinity Ordering Information Part Number R/W Cycle Time 25 ns 35 ns Package 24-pin plastic SOP (11.43 mm (450)) µPD485505G-25 µPD485505G-35 The information in this document is subject to change without notice. Before usin...