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MBM30LV0064 Dataheets PDF



Part Number MBM30LV0064
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description 64M (8M X 8) BIT NAND-type
Datasheet MBM30LV0064 DatasheetMBM30LV0064 Datasheet (PDF)

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20878-3E FLASH MEMORY CMOS 64M (8M × 8) BIT NAND-type MBM30LV0064 s DESCRIPTION The MBM30LV0064 device is a single 3.3 V 8M × 8 bit NAND flash memory organized as 528 byte × 16 pages × 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code(Specifications indecated are on condition that ECC system would be combined.). Program and read data is transferred between the memory array and page reg.

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20878-3E FLASH MEMORY CMOS 64M (8M × 8) BIT NAND-type MBM30LV0064 s DESCRIPTION The MBM30LV0064 device is a single 3.3 V 8M × 8 bit NAND flash memory organized as 528 byte × 16 pages × 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code(Specifications indecated are on condition that ECC system would be combined.). Program and read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page can be programmed in 200 µs and an 8K byte block can be erased in 2 ms under typical conditions. An internal controller automates all program and erase operations including the verification of data margins. Data within a page can be read with a 50 ns cycle time per byte. The I/O pins are utilized for both address and data input/ output as well as command inputs. The MBM30LV0064 is an ideal solution for applications requiring mass nonvolatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage. s PRODUCT LINE UP Part No. Operating Temperature VCC Read Power Dissipation (Max.) Erase / Program TTL Standby CMOS Standby MBM30LV0064 –40°C to +85°C +2.7 V to +3.6 V 72 mW 72 mW 3.6 mW 0.18 mW s PACKAGES 44-pin plastic TSOP (II) Marking Side Marking Side (FPT-44P-M07) (Normal Bend) (FPT-44P-M08) (Reverse Bend) MBM30LV0064 s FEATURES • 3.3 V-only operating voltage (2.7 V to 3.6 V) Minimizes system level power requirements • Organization Memory Cell Array : (8M + 256K) ×8 bit Data Register : (512 + 16) ×8 bit • Automatic Program and Erase Page Program : (512 + 16) Byte Block Erase : (8K + 256) Byte • 528 Byte Page Read Operation Random Access : 7 µs (Max.) Serial Access : 35 ns (Max.) • Fast Program and Erase Program Time : 200 µs (Typ.) / page Block Erase Time : 2 ms (Typ.) / block • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection • 1,000,000 write/erase cycle guaranteed (ECC system required) • Command Register Operation • Package 44(40)-pin TSOP Type II (0.8 mm pitch) Normal/Reverse Type • Data Retention: 10 years 2 MBM30LV0064 s PIN ASSIGNMENTS TOP VIEW Vss CLE ALE WE WP N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss 13 14 15 16 17 18 19 20 21 22 FPT-44P-M07 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq N.C. N.C. N.C. N.C. N.C. I/O7 I/O6 I/O5 I/O4 Vccq Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. Vcc CE RE R/B SE N.C. N.C. N.C. N.C. N.C. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 FPT-44P-M08 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 N.C. N.C. N.C. N.C. N.C. I/O0 I/O1 I/O2 I/O3 Vss Vss CLE ALE WE WP N.C. N.C. N.C. N.C. N.C. 3 MBM30LV0064 s PIN DESCRIPTIONS Pin Number Pin Name 18 to 21 24 to 27 I/O0 to I/O7 Descriptions Data Input/Output The I/O ports are used for transferring command, address, and input/output data into and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected. Command Latch Enable The CLE signal enables the acquisition of the made command into the internal command register. When CLE=“H”, command are latched into the command register from the I/O port upon the rising edge of the WE signal. Address Latch Enable The ALE signal enables the acquisition of either address or data into the internal address/data register. The rising edge of WE latch in addresses when ALE is high and data when ALE is low. Chip Enable The CE signal is used to select the device. When CE is high, the device enters a low power standby mode. If CE transitions high during a read operation, the standby mode will be entered. However, the CE signal is ignored if the device is in a busy state(R/B=L) during a program or erase operation. Read Enable The RE signal controls the serial data output. The falling edge of RE drives the data onto the I/O bus and increments the column address counter by one. Write Enable The WE signal controls writes from the I/O port. Data, address, and commands on the I/O port are latched upon the rising of the WE pulse. Write Protect The WP signal protects the device against accidental erasure or programming during power up/down by disabling the internal high voltage generators. WP should be kept low when the device powers up until VCC is above 2.5 V. During power down, WP should be low when VCC falls below 2.5 V. Spare Area Enable The SE input enables the spare area during sequential data input, page program, and Read 1. Ready Busy Output The R/B output signal is used to indicate the operating status of the device. During program, erase, or read, R/B is low and will return high upon the completion of the operation. The output buffer for this signal is an open drain. Output Buffer Power Supply The VCCq input.


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