SY10EL51

Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS DIFFERENTIAL CLOCK D FLIP-FLOP SY10EL51 SY1S0YE10L05E1L51 SY100EL51 FEATURES s 475ps propagation delay s 2.8GHz toggle frequency s Internal 75KΩ input pull-down resistors s Available in 8-pin SOIC package DESCRIPTION The SY10/100EL51 are differential clock D flip-flops with reset. These devices are functionally similar to the E151 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E151, the EL51 is ideally suited for those applications which require the ultimate in AC performance. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input (pulled down to VEE) conditions. PIN NAMES Pin R D CLK Q Function Reset Input Data Input Clock Input Data Output TRUTH TABLE(1) DR LL HL XH NOTE: 1. Z = LOW-to-HIGH transition. CLK Z Z X Q L H L M9999-121205 hbwhelp@micrel.com or (408) 955-1690 11 Rev.: G Amendment: /0 Issue Date: December 2005 Micrel, Inc. SY10EL51 SY100EL51 PACKAGE/ORDERING INFORMATION Ordering Information(1) R1 D2 CLK 3 CLK 4 R D Flip-Flop 8-Pin SOIC (Z8-1) 8 VCC 7Q 6Q 5 VEE ...