DM74LS192

54LS192 DM74LS192 Up Down Decade Counter with Separate Up Down Clocks May 1992 54LS192 DM74LS192 Up Down Decade Counter with Separate Up Down Clocks General Description The ’LS192 is an up down BCD decade (8421) counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronous with the LOW-toHIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stage without extra logic thus simplifying multistage counter designs Individual preset inputs allow the circuits to be used as programmable counters Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Connection Diagram Dual-In-Line Package Logic Symbol TL F 10178 – 2 VCC e Pin 16 GND e Pin 8 TL F 10178 – 1 Order Number 54LS192DMQB 54LS192FMQB 54LS192LMQB DM74LS192M or DM74LS192N See NS Package Number E20A J16A M16A N16E or W16A Pin Names CPU CPD MR PL P0 – P3 Q0 – Q3 TCD TCU Description Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW) MR H L L L L PL X L H H H Mode Select Table CPU X X H L H CPD X X H H L Mode Reset (Asyn ) Preset (A...