CY7C374

For new designs see CY7C374i CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Features 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed — fMAX = 100 MHz — tPD = 12 ns — tS = 6 ns — tCO = 7 ns Electrically Alterable Flash technology Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP, and 84-pin PGA packages Pin compatible with the CY7C373 Functional Description The CY7C374 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of high-density, high-speed CPLDs. Like all members of the FLASH370 family, the CY7C374 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. The 128 macrocells in the CY7C374 are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. The CY7C374 is a register intensive 128-Macrocell CPLD. Every two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374. In addition, there are two dedicated inputs and four input/clock pins. Logic Block Diagram CLOCK INPU...