Document
PL-2305 USB to IEEE 1284 Bridge Controller Product Datasheet
Document Revision 1.1 Document Release: August, 2002
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Prolific Technology Inc.
www.DataSheet4U.com
Release Date: August, 2002 ds_pl2305_v11
PL-2305 USB to IEEE 1284 Bridge Controller
1.0 Features
Full compliance with the Universal Serial Bus Specification Version 1.1 Full compliance with the Universal Serial Bus Device Class Definition for Printing Devices Version 1.0 Full compliance with the IEEE std 1284-1994 – “IEEE Standard Signaling Method for a Bi-directional Parallel Peripheral Interface for Personal Computers” On chip transceivers and regulator for USB interface Fully automatic high speed bi-directional communication over parallel port 512 Bytes unified data buffer dynamically allocated for upstream and downstream data transfer Drivers provided for Microsoft Windows 98/NT 5.0
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Figure 1.
PL-2305 Block Diagram
PL-2305 Product Datasheet
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Document Revision 1.1
Release Date: August, 2002 ds_pl2305_v11
2.0 Overview
The PL-2305 integrated circuit provides a high-speed bi-directional bridge between the Universal Serial Bus (USB) system and IEEE-1284 parallel port peripheral devices. It is designed to be a flexible, high performance, and low-cost single-chip solution for USB cable as well as USB ready peripheral manufacturers.
Supporting for multi-function devices, such as Printer-FAX-Scanner-Copier all-in-one device, is one of the major design considerations of PL-2305. It provides well-balanced bi-directional data transferring. Retrieving data from external device could be as efficient as transmitting data through this chip.
Ease of programming is another major design consideration of PL-2305. The vendor specific requests of PL-2305 are so defined to reduce the USB bus traffic and hence minimize the host software overhead.
The external serial EEPROM support gives the user of PL-2305 options to customize this chip to show their identity. The user could modify the Vendor ID, Product ID, Language ID, manufacturer string, product string, and serial number strings of the final product. They could also use this EEPROM to store authorization/security codes. For large quantity orders, it is also possible to modify the Maskable ROM (Read Only Memory) of PL-2305 to better represent the final product manufacturer and thus eliminate the need for external EEPROM.
PL-2305 Product Datasheet
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Document Revision 1.1
Release Date: August, 2002 ds_pl2305_v11
3.0 Pin Description
GND Reserved Reserved XTEST XIN XOUT PLLVCC PLLTEST PLLGND SUSPEND USBGND DMINUS DPLUS USBVCC ZREGVCC VCC RESETJ NC RWAKEUPJ NC SCL SDA NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 (300 mil) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 XPLH XATFJ XSEL XPERR XBUSY XACKJ PD7 VCC NC PD6 PD5 NC PD4 NC PD3 PD2 GND NC PD1 PD0 XSTBJ XINIJ XFLTJ XSLIJ
Figure 2. PL-2305 Pin Diagram
Table 1. Pins Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND Reserved Reserved XTEST XIN XOUT PLLVCC PLLTEST PLLGND NC USBGND DMINUS DPLUS USBVCC ZREGVCC VCC Type P – – I I O P I P – P I/O I/O P P P Description Ground. Reserved, must be tied to ground. Reserved, must be tied to ground. Core test pin must be tied to ground for normal operation. Crystal in or CMOS oscillator input. Crystal out or no connection. 5V Analog Power Supply for on-chip PLL. PLL test pin must be tied to ground for normal operation. Analog Ground for on-chip PLL. No connection. Ground for on-chip USB transceiver. USB D- signal. USB D+ signal. 3.3V Power Supply for on-chip USB transceiver. 3.3V output from on-chip 5V-to-3.3V regulator. 5V Power Supply for on-chip 5V-to-3.3V regulator.
PL-2305 Product Datasheet
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Document Revision 1.1
Release Date: August, 2002 ds_pl2305_v11
Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Type:
Symbol RESETJ NC RWAKEUPJ NC SCL SDA NC VCC XSLIJ XFLTJ XINIJ XSTBJ PD0 PD1 NC GND PD2 PD3 NC PD4 NC PD5 PD6 NC VCC PD7 XACKJ XBUSY XPERR XSEL XATFJ XPLH
I – Input signal
Type I – I – I/O I/O – P O I O O I/O I/O – P I/O I/O – I/O – I/O I/O – P I/O I I I I O I
Description Optional external Power-On-Reset signal. No connection. USB Remote Wake enable, tied to VCC if no remote wake up control is available.* N.