(PI6C41202 / PI6C41204) LVCMOS to LVPECL Driver
PI6C41202 PI6C41204 PI6C41204A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345...
Description
PI6C41202 PI6C41204 PI6C41204A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
LVCMOS to LVPECL Driver
Features
Up to Four LVPECL outputs Selectable CLK0 or CLK1 inputs LVCMOS or LVTTL input level 30ps max output skew 150ps max part-to-part skew 1.9ns max propagation delay 266 MHz output frequency Packaging (Pb-free & Green available): -14-pin TSSOP - 20-pin TSSOP
Description
PI6C4120x is a high-performance LVCMOS or LVTTL to LVPECL clock buffer. The PI6C41204 is a 4 output version with 2 selectable inputs, pin compatible with ICS8535-01. PI6C41204A is the enhanced version with extra power and ground pins to minimize noise and jitter. The PI6C41202 is similar to the PI6C41204 except it has two outputs.
Block Diagram PI6C41204/A
CLK_EN CLK0 CLK1 0 1 D LE Q Q0 nQ0 Q1 CLK_SEL nQ1 Q2 nQ2 Q3 nQ3
Pin Configuration PI6C41204/A
Vee CLK_EN CK_SEL CLK0 nc/Vee CLK1 nc/Vee nc/Vee nc/Vcc Vcc
1 2 3 4 5 6 7 8 9 10 20 19 18 17
20-Pin
16 15 14 13 12 11
Q0 nQ0 Vcc Q1 nQ1 Q2 nQ2 Vcc Q3 nQ3
Block Diagram PI6C41202
D CLK_EN LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q
Pin Configuration PI6C41202
Vee CLK_EN CK_SEL CLK0 Vee CLK1 Vcc
1 2 3 4 5 6 7 14 13
14-Pin 12
11 10 9 8
Vcc Q0 nQ0 nc Q1 nQ1 Vcc
1
PS8626D
05/11/05
123456789012345678901234567...
Similar Datasheet