IBM25PPC405GPR

Preliminary PowerPC 405GPr Embedded Processor Data Sheet Features IBM PowerPC 405 32-bit RISC processor core operating up to 400MHz with 16KB I- and D-caches PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications 4KB on-chip memory (OCM) Programmable timers External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) Two serial ports (16550 compatible UART) One IIC interface General purpose I/O (GPIO) available Supports JTAG for board level testing Internal processor local Bus (PLB) runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory Unique software-accessible 64-bit chip ID number (ECID). - Synchronous or asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) Programmable interrupt controller supports 13 external and 19 internal edge triggered or levelsensitive interrupts Description Designed specifically to address embedded applications, the PowerPC 405GPr (PPC405GPr) provides a high-performance, low-power solution that ...