39VF6401 SST39VF6401 Datasheet

39VF6401 Datasheet PDF, Equivalent


Part Number

39VF6401

Description

SST39VF6401

Manufacture

Silicon Storage Technology

Total Page 30 Pages
Datasheet
Download 39VF6401 Datasheet


39VF6401
16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
FEATURES:
Preliminary Specifications
• Organized as 1M x16: SST39VF1601/1602
2M x16: SST39VF3201/3202
4M x16: SST39VF6401/6402
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF1602/3202/6402
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF1601/3201/6401
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
– 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm) for 16M and 32M
– 48-ball TFBGA (8mm x 10mm) for 64M
PRODUCT DESCRIPTION
The SST39VF160x/320x/640x devices are 1M x16, 2M
x16, and 4M x16 respectively, CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared
with alternate approaches. The SST39VF160x/320x/640x
write (Program or Erase) with a 2.7-3.6V power supply.
These devices conform to JEDEC standard pinouts for
x16 memories.
Featuring high performance Word-Program, the
omSST39VF160x/320x/640x devices provide a typical Word-
.cProgram time of 7 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
t4ution. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
eDesigned, manufactured, and tested for a wide spectrum of
eapplications, these devices are offered with a guaranteed
shtypical endurance of 100,000 cycles. Data retention is rated
taat greater than 100 years.
w.da©2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
ww 1
The SST39VF160x/320x/640x devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

39VF6401
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
To meet high density, surface mount requirements, the
SST39VF160x/320x/640x are offered in 48-lead TSOP
and 48-ball TFBGA packages. See Figures 1 and 2 for
pin assignments.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF160x/320x/640x also have the Auto Low
Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the IDD active read current from
typically 9 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDD active read current to the range of 2
mA/MHz of Read cycle time. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter
Auto-Low Power mode after power-up with CE# held
steadily low, until the first address transition or CE# is
driven high.
Read
The Read operation of the SST39VF160x/320x/640x is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 3).
Word-Program Operation
The SST39VF160x/320x/640x are programmed on a
word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program
operation is accomplished in three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is
the internal Program operation which is initiated after the
rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted within 10 µs. See Figures 4 and 5 for WE# and CE#
controlled Program operation timing diagrams and Figure
19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command
sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF160x/320x/640x offer both Sec-
tor-Erase and Block-Erase mode. The sector architecture
is based on uniform sector size of 2 KWord. The Block-
Erase mode is based on uniform block size of 32 KWord.
The Sector-Erase operation is initiated by executing a six-
byte command sequence with Sector-Erase command
(30H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
and block address (BA) in the last bus cycle. The sector or
block address is latched on the falling edge of the sixth
WE# pulse, while the command (30H or 50H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
©2003 Silicon Storage Technology, Inc.
2
S71223-03-000
11/03


Features 16 Mbit / 32 Mbit / 64 Mbit (x16) Multi- Purpose Flash Plus SST39VF1601 / SST39V F3201 / SST39VF6401 SST39VF1602 / SST39 VF3202 / SST39VF6402 SST39VF160x / 320 x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) M PF+ memories FEATURES: Preliminary Spe cifications • Organized as 1M x16: S ST39VF1601/1602 2M x16: SST39VF3201/320 2 4M x16: SST39VF6401/6402 • Single V oltage Read and Write Operations – 2. 7-3.6V • Superior Reliability – End urance: 100,000 Cycles (Typical) – Gr eater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typ ical) – Standby Current: 3 µA (typic al) – Auto Low Power Mode: 3 µA (typ ical) • Hardware Block-Protection/WP# Input Pin – Top Block-Protection (to p 32 KWord) for SST39VF1602/3202/6402 Bottom Block-Protection (bottom 32 K Word) for SST39VF1601/3201/6401 • Sec tor-Erase Capability – Uniform 2 KWor d sectors • Block-Erase Capability Uniform 32 KWord blocks • Chip-Erase Capability • Erase-Suspend/Erase-Resume Capabilities • Hardw.
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