74C910 MM74C910 Datasheet

74C910 Datasheet PDF, Equivalent


Part Number

74C910

Description

MM74C910

Manufacture

National Semiconductor

Total Page 8 Pages
PDF Download
Download 74C910 Datasheet PDF


74C910
September 1989
MM54C910 MM74C910 256 Bit TRI-STATE
Random Access Read Write Memory
General Description
The MM54C910 MM74C910 is a 64 word by 4-bit random
access memory Inputs consist of six address lines four
data input lines a WE and a ME line The six address lines
are internally decoded to select one of the 64 word loca-
tions An internal address register latches the address infor-
mation on the positive to negative transition of ME The
TRI-STATE outputs allow for easy memory expansion
Address Operation Address inputs must be stable (tSA)
prior to the positive to negative transition of ME and (tHA)
after the positive to negative transition of ME The address
register holds the information and stable address inputs are
not needed at any other time
Write Operation Data is written into memory at the select-
ed address if WE goes low while ME is low WE must be
held low for tWE and data must remain stable tHD after WE
returns high
Read Operation Data is nondestructively read from a
memory location by an address operation with WE held
high
Outputs are in the TRI-STATE (Hi-Z) condition when the
device is writing or disabled
Features
Y Supply voltage range
Y High noise immunity
Y TTL compatible fan out
Y Input address register
Y Low power consumption
Y Fast access time
Y TRI-STATE outputs
Y High voltage inputs
3 0V to 5 5V
0 45VCC (typ )
1 TTL load
250 nW package (typ )
(chip enabled or disabled)
250 ns (typ ) at 5 0V
Logic Diagrams
www.DataSheet4U.com
Input Protection
u.comTRI-STATE is a registered trademark of National Semiconductor Corporation
www.datasheet4C1995 National Semiconductor Corporation TL F 5914
TL F 5914– 1
TL F 5914– 2
RRD-B30M105 Printed in U S A

74C910
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Output Pin
Voltage at Any Input Pin
b0 3V to VCC a0 3V
b0 3V to a15V
Power Dissipation
Dual-In-Line
Small Outline
700 mW
500 mW
Operating VCC Range
Standby VCC Range
Absolute Maximum (VCC)
Lead Temperature (TL)
(Soldering 10 sec )
3 0V to 5 5V
1 5V to 5 5V
6 0V
260 C
Operating Conditions
Min
Supply Voltage (VCC)
MM54C910
MM74C910
45
4 75
Temperature (TA)
MM54C910
MM74C910
b55
b40
Max
55
5 25
a125
a85
DC Electrical Characteristics
Min Max limits apply accross the temperature and power supply range indicated
Symbol
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VOUT(1)
VOUT(0)
IOZ
ICC
Parameter
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Output Current in High
Impedance State
Supply Current
Conditions
Full Range
Full Range
VIN e 15V
VIN e 5V
VIN e 0V
IO e b150 mA
IO e b400 mA
IO e 1 6 mA
VO e 5V
VO e 0V
VCC e 5V
Min
VCC b 1 5
b1 0
VCC b 0 5
24
b1 0
Typ
0 005
0 005
b0 005
0 005
b0 005
50
Max
08
20
10
04
10
300
Units
V
V
C
C
Units
V
V
mA
mA
mA
V
V
V
mA
mA
mA
AC Electrical Characteristics TA e 25 C VCC e 5 0V CL e 50 pF
Symbol
Parameter
Min Typ Max Units
tACC
Access Time from Address
250 500
tpd Propagation Delay from ME
180 360
tSA
Address Input Set-Up Time
140 70
tHA Address Input Hold Time 20 10
tME
Memory Enable Pulse Width
200 100
tME
Memory Enable Pulse Width
400 200
tSD Data Input Set-Up Time
0
tHD Data Input Hold Time
30 15
tWE
Write Enable Pulse Width
140 70
t1H t0H
Delay to TRI-STATE (Note 4)
100 200
CAPACITANCE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CIN Input Capacity
Any Input (Note 2)
5 0 pF
COUT
Output Capacity
Any Output (Note 2)
9 0 pF
CPD Power Dissipation Capacity 350 pF
(Note 3)
2


Features MM54C910 MM74C910 256 Bit TRI-STATE Rand om Access Read Write Memory September 1989 MM54C910 MM74C910 256 Bit TRI-STA TE Random Access Read Write Memory Gen eral Description The MM54C910 MM74C910 is a 64 word by 4-bit random access mem ory Inputs consist of six address lines four data input lines a WE and a ME li ne The six address lines are internally decoded to select one of the 64 word l ocations An internal address register l atches the address information on the p ositive to negative transition of ME Th e TRI-STATE outputs allow for easy memo ry expansion Address Operation Address inputs must be stable (tSA) prior to th e positive to negative transition of ME and (tHA) after the positive to negati ve transition of ME The address registe r holds the information and stable addr ess inputs are not needed at any other time Write Operation Data is written in to memory at the selected address if WE goes low while ME is low WE must be he ld low for tWE and data must remain stable tHD after WE returns.
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