Document
STP4NB50 STP4NB50FP
N-CHANNEL 500V - 2.5Ω - 3.8A - TO-220/TO-220FP PowerMesh™ MOSFET
PRELIMINARY DATA TYPE STP4NB50 STP4NB50FP
s s s s s
VDSS 500 V 500 V
RDS(on) < 2.8 Ω < 2.8 Ω
ID 3.8 A 2.5 A
TYPICAL RDS(on) = 2.5 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED TO-220
3 1 2
3 1 2
DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE
s
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt VISO Tstg Tj Parameter STP4NB50 Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature –65 to 150 150
(1)ISD ≤4 A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
Value STP4NB50FP 500 500 ±30 3.8 2.4 15.2 80 0.64 4.5 2500 2.5 1.6 15.2 35 0.28
Unit V V V A A A W W/°C V/ns V °C °C
(•)Pulse width limited by safe operating area
April 2003
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THERMAL DATA
TO-220 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1.56 62.5 300 TO-220FP 3.57 °C/W °C/W °C
AVALANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 3.8 220 Unit A mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ±30V Min. 500 1 50 ±100 Typ. Max. Unit V µA µA nA
ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250µA VGS = 10V, ID = 1.9 A Min. 2 Typ. 3 2.5 Max. 4 2.8 Unit V Ω
DYNAMIC
Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 1.9 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 2.3 400 62 7.5 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 250V, ID = 1.9 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 3.8 A, VGS = 10V Min. Typ. 11 8 15 6.5 5 21 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400V, ID = 3.8 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. Typ. 8 5 14 Max. Unit ns ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3.8 A, VGS = 0 ISD = 3.8 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 245 980 9 Test Conditions Min. Typ. Max. 3.8 15.2 1.6 Unit A A V ns nC A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-220 MECHANICAL DATA
mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 øP Q
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TO-220FP MECHANICAL DATA
mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1..