ICS1524

Integrated Circuit Systems, Inc. ICS1524 Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description The ICS1524 is a low-cost, very high-performance frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock synthesis and distribution as well as line-locked and genlocked applications. The ICS1524 offers two channels of clock phase controlled outputs; CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL’s input and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input signal. Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal programmable feedback divider or an external divider and is programmed by a standard I2C-bus™ serial interface. Features Wide input frequency range 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock outputs Dynamic Phase Adjust (DPA) for DPACLK outputs Software controlled phase adjustment 360o Adjustment down to 1/64 clock increments ...