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MC54HC4353 Dataheets PDF



Part Number MC54HC4353
Manufacturers Motorola
Logo Motorola
Description (MC54HC4351 / MC54HC4353) Analog Multiplexers/Demultiplexers
Datasheet MC54HC4353 DatasheetMC54HC4353 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Analog Multiplexers/ Demultiplexers with Address Latch MC54/74HC4351 MC54/74HC4353 High–Performance Silicon–Gate CMOS The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel–Select inputs determine which o.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Analog Multiplexers/ Demultiplexers with Address Latch MC54/74HC4351 MC54/74HC4353 High–Performance Silicon–Gate CMOS The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel–Select inputs determine which one of the Analog Inputs/ Outputs is to be connected, by means of an analog switch, to the Common Output/Input. The data at the Channel–Select inputs may be latched by using the active–low Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches. For multiplexers/demultiplexers without latches, see the HC4051, HC4052, and HC4053. • • • • • • • • Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance than Metal–Gate Types Low Noise In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates HC4353 — 186 FETs or 46.5 Equivalent Gates 20 1 J SUFFIX CERAMIC PACKAGE CASE 732–03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDW Ceramic Plastic SOIC PIN ASSIGNMENT MC54/74HC4351 X4 X6 NC X X7 X5 ENABLE 1 ENABLE 2 VEE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC X2 X1 X0 X3 A NC B C LATCH ENABLE NC = NO CONNECTION 10/95 © Motorola, Inc. 1995 1 REV 6 MC54/74HC4351 MC54/74HC4353 LOGIC DIAGRAM MC54/74HC4351 Single–Pole, 8–Position Plus Common Off and Address Latch 17 X0 18 X1 19 X2 16 X3 1 X4 6 X5 2 X6 5 X7 FUNCTION TABLE MC54/74HC4351 MULTIPLEXER/ DEMULTIPLEXER 4 X COMMON OUTPUT/INPUT Control Inputs Enable 1 2 C Select B A ON Channel (LE = H)* ANALOG INPUTS/OUTPUTS CHANNEL–SELECT INPUTS A B C 15 13 12 11 7 8 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 L H L L L X0 L H L L H X1 L H L H X2 L L H L H H X3 L H H X4 L L L L H H H X5 L H H H X6 L L H H H H X7 H None X X X X X None L X X X X = don’t care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. BLOCK DIAGRAM MC54/74HC4353 Triple Single–Pole, Double–Position Plus Common Off and Address Latch 16 X0 17 X1 Y0 Y1 Z0 Z1 15 13 12 11 7 8 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 2 1 6 4 PIN ASSIGNMENT X SWITCH 18 X COMMON OUTPUT/INPUT Y1 Y0 NC Z1 Z SWITCH 5 Z Z Z0 ENABLE 1 ENABLE 2 VEE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Y X X1 X0 A NC B C LATCH ENABLE Y SWITCH 19 Y CHANNEL–SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 NC = NO CONNECTION FUNCTION TABLE Control Inputs Enable 1 L L L L L L L L H X 2 H H H H H H H H X L C L L L L H H H H X X Select B L L H H L L H H X X A L H L H L H L H X X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 On Channel (LE = H)* Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None None X0 X1 X0 X1 X0 X1 X0 X1 NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X Switch, Input B controls the Y Switch, and Input C controls the Z Switch. X = Don’t Care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. MOTOROLA 2 High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol VCC VEE VIS Vin I PD Parameter Value Unit V V V V Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) – 0.5 to + 7.0 – 0.5 to 14.0 – 7.0 to + 0.5 VEE – 0.5 to VCC + 0.5 ± 25 750 500 Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage DC Input Voltage (Ref. to GND) – 1.5 to VCC + 1.5 DC Current Into or Out of Any Pin mA Power Dissipation in Still.


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