XC2C64

0 R XC2C64 CoolRunner-II CPLD 0 0 DS092 (v1.0) December 19, 2001 Advance Product Specification Features Industries best 0.18 micron CMOS CPLD - 4.0 ns pin-to-pin logic delays - less than 100 µA standby current consumption - 64 macrocells with up to 1,600 logic gates - Fast input registers - Slew rate control on individual outputs - LVCMOS 1.8V through 3.3V - LVTTL 3.3V Available in multiple package styles - 44-pin PLCC with 33 user I/O - 44-pin VQFP with 33 user I/O - 56-ball CP (0.05mm) BGA with 45 user I/O - 100-pin VQFP with 64 user I/O Optimized for high performance 1.8V systems - Ultra low power operation - Advanced 0.18 micron 4-metal layer Non-volatile process Advanced system features - Quadruple enhanced security - Multi-voltage system interface - Hot pluggable - IEEE1532 In-system programmable - Superior pin locking through PLA array - Input hysteresis (Schmitt trigger) on all pins - Bus hold circuitry on all user pins - IEEE standard 1149.1 boundary scan (JTAG) - Fast programming times - Excellent pin retention during design changes - High quality and reliability - Guaranteed 10,000 program/erase cycles - 20 year data retention Description The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and speed to battery operated devices. This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM ...