SC680E

APPROVED PRODUCT SC680E SMBus System Clock Buffer Product Features § § § § § § § 18 output buffer for high clock fanout applications Each output can be internally disabled for EMI reduction VDD=3.3 volts for chip Vdd Output frequency range 10 Mhz to 100 Mhz < 250ps skew between output clocks 48-pin SSOP package Single Clock Enable pin for testability Product Description The SC680 is a high fanout system clock buffer. Its primary application is to create the large quantity of clocks needed to support a wide range of applications that requires those clock loads signal that are referenced to a single existing clock. Loads of up to 30 pF are supported. One of the chief applications of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces. Using these devices EMI is therefore minimized and board real estate is saved. Block Diagram VDD CLK[1:2] VDD CLK[3:4] REFIN VDD CLK[5:6] VDD CLK[7:8] VDD CLK[9:10] VDD CLK[11:12] OE SDATA SCLK VDD Pin Configuration IMISC680 NC NC VDD CLK1 CLK2 VSS VDD CLK3 CLK4 VSS REFIN VDD CLK[15:16] VDD CLK[17,18] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC VDD CLK18 CLK17 VSS VDD CLK15...