Secure Microcontroller. AT91SO100 Datasheet

AT91SO100 Datasheet PDF, Equivalent


Part Number

AT91SO100

Description

(AT91SO101 / AT91SO101) Secure Microcontroller

Manufacture

ATMEL Corporation

Total Page 4 Pages
PDF Download
Download AT91SO100 Datasheet PDF


AT91SO100 Datasheet
Features
General
High-performance, Low-power 32-bit ARM®-SC100Enhanced RISC Architecture
Von Neumann Load / Store Architecture
– single 32-bit Data Bus for Instructions and Data
Memory Protection unit
Internal Oscillator (VFO) (up to 50 MHz)
ESD Protection to ± 2000V (± 6000V on the ISO interfaces)
Operating Ranges: 3.3V (+/- 10%)
Compliant with EMV Level 1, VISA PED, APACS, ZKA, Common Criteria (EAL4+),
FINREAD
Memory
256 bits of Key Storage (battery backup)
32K Bytes of internal ROM Memory (BOOT, library)
256K Bytes of Internal EEPROM, Including 128 OTP Bytes and 384-byte Bit-
addressable Bytes
1 to 128-byte Program/Erase
2 ms Program, 2 ms Erase
Endurance: 500,000 Write/Erase Cycles at temperature of 25 degrees C
10 Years Data Retention
100K Bytes of Internal RAM (4KB Crypto RAM)
up to 16M Bytes of External Memory (accessed by page)
Peripherals
Page Unit to access External Memory Page
Static Memory Controller
Two ISO 7816 controllers with DC/DC (one of them can be multiplexed to address 4
SAM)
USB 2.0 Full Speed (8 endpoints)
SPI Controller (up to 24 Mbps)
Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Triple Track Magstripe Logical Interface
5 8-bit I/O Port Interface (LEDs, Keyboard, LCD, spare...)
Real Time Clock (RTC) with Alarm interrupt
System Timer including a 16-bit Counter, Watchdog and Second Counter
Six-channel 16-bit Timer/counter
2-level, 28-interrupt Controller
Hardware DES and Triple DES DPA Resistant
Hardware AES 128-192-256
Hardware SHA-1, SHA-256
True Random Number Generator (RNG)
Two CRC 16 Engines and one CRC 32 Engine (Compliant with ISO/IEC 3309)
AdvX - Advanced crypto multiplier for cryptography and authentication (including
RSA, DSA, Key Generation, ECC)
Secure
Microcontroller
for Electronic
Transaction
Terminal /
Reader
AT91SO100/101
Summary
Security
mDedicated Hardware for Protection Against SPA/DPA Attacks
oAdvanced Protection Against Physical Attack, Including Active Shield
.cIntrusion sensors (mesh and switches).
Environmental Protection Systems (Voltage, Frequency, UV andTemperature)
t4uSecure Memory Management/Access Protection (MPU)
Real time clock and battery back up
eeCompliant with EMV standard, VISA PED and FINREAD
6514BS–SMIC–26Oct05
tash Note: This is a summary document. A complete document will be
a available under NDA. For more information, please contact your
www.d local Atmel sales office.

AT91SO100 Datasheet
Description
AT91SO100 is a low-power, high-performance, SC100 32-bit microcontroller based on the ARM® enhanced RISC architecture. This new
SC100 core allows the linear addressing of up to 1M bytes of code and data as well as a number of new functional and security features.
A 3-level instruction pipeline allows the performance of one instruction in a single clock cycle, the AT91SO100 achieves throughputs
close to 1 MIPS per MHz. The SC100 processor employs a unique architectural strategy known as Thumb® a super reduced instruction
set that is ideally suited for high volume applications with memory restrictions and applications where code density is an important factor.
AT91SO100 has internal EEPROM that can be used as program or data memory. It also includes a ROM (for the boot and some native
functions) and a large SRAM. AT91SO100 can also address, via pages, up to 16Mbytes of external memory.
The AT91SO100 also comprises of strong security mechanisms and has a impressive set of crytography features , hardware DES/TDES,
hardware AES, hardware SHA-n, hardware cryptography accelerator for asymmetric algorithms (RSA, Elliptic Curve, Key generation)
and a true random number generator.
AT91SO100 includes a lot of dedicated peripherals as smart card and magnetic stripe card interface, as well as USB, SPI,
UARTs and I/O ports.
The AT91SO101 is a single package solution in BGA256 embedding two chips, the AT91SO100 and the AT83C26 which
physically interface with up to five smart cards.
2 AT91SO100
6514BS–SMIC–26Oct05


Features Datasheet pdf Features General • High-performance, L ow-power 32-bit ARM®-SC100 Enhanced RISC Architecture • Von Neumann Load / Store Architecture • • • • – single 32-bit Data Bus for Instr uctions and Data Memory Protection unit Internal Oscillator (VFO) (up to 50 MH z) ESD Protection to ± 2000V (± 6000V on the ISO interfaces) Operating Range s: 3.3V (+/- 10%) Compliant with EMV Le vel 1, VISA PED, APACS, ZKA, Common Cri teria (EAL4+), FINREAD Memory • 256 bits of Key Storage (battery backup) 32K Bytes of internal ROM Memory (BOO T, library) • 256K Bytes of Internal EEPROM, Including 128 OTP Bytes and 384 -byte Bitaddressable Bytes – 1 to 128 -byte Program/Erase – 2 ms Program, 2 ms Erase – Endurance: 500,000 Write/ Erase Cycles at temperature of 25 degre es C – 10 Years Data Retention • 10 0K Bytes of Internal RAM (4KB Crypto RA M) • up to 16M Bytes of External Memo ry (accessed by page) Secure Microcont roller for Electronic Transaction Terminal / Reader AT91SO100/101 Summary Peripherals • Page Unit to .
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