IN74AC175

TECHNICAL DATA Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS The IN74AC175 is identical in pinout to the LS/ALS175, HC/HCT175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positivegoing edge of the Clock input. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 mA IN74AC175 ORDERING INFORMATION IN74AC175N Plastic IN74AC175D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Reset PIN 16=VCC PIN 8 = GND L H H H X = Don’t care L Clock X D X H L X Outputs Q L H L Q H L H w w w .d h s a t a ee . u t4 m o c no change 1 www.DataSheet4U.com IN74AC175 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Packa...