Dual J-K Positive-Edge-Triggered Flip-Flop
TECHNICAL DATA
IN74AC109
Dual J-K Flip-Flop with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC109 is identical...
Description
TECHNICAL DATA
IN74AC109
Dual J-K Flip-Flop with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 mA
ORDERING INFORMATION IN74AC109N Plastic IN74AC109D SOIC TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Set L H L H H Reset H L L H H H H Clock X X X J X X X L H L H K X X X L L H H Outputs Q H L H
*
Q L H H* H
L
Toggle No Change H L
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w
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e e h s a t a
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PIN 16=VCC PIN 8 = GND
m o c
H H
H H L X X No Change X = Don’t care * Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
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IN74AC109
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to G...
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