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TECHNICAL DATA
IN74HCT240A
Octal 3-State Inverting Buffer/Line Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The IN74HCT240A is identical in pinout to the LS/ALS240. The IN74HCT240A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other busoriented systems. The device has inverting outputs and two active-low output enables. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA
ORDERING INFORMATION IN74HCT240AN P lastic IN74HCT240ADW SOIC TA = -55° to 125° C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Outputs A,B L H X YA,YB H L Z
w
w
w
.d
h s a t a
ee
. u t4
m o c
PIN 20=VCC PIN 10 = GND
Enable A, Enable B L L H
X = don’t care Z = high impedance
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IN74HCT240A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260
Unit V V V mA mA mA mW °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IN74HCT240A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 ±0.5 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 ±5.0 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 ±1.0 ±10.0 µA µA V Unit
VIH VIL VOH
Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage
VOUT=0.1 V ⎢IOUT⎢≤ 20 µA VOUT= VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA VIN= VIL ⎢IOUT⎢ ≤ 20 µA VIN=VIL ⎢IOUT⎢ ≤ 6.0 mA
4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
V V V
VOL
Maximum LowLevel Output Voltage
VIN=VIH ⎢IOUT⎢ ≤ 20 µA VIN= VIH ⎢IOUT⎢ ≤ 6.0 mA
IIN IOZ
Maximum Input Leakage Current Maximum three State Leakage Current
VIN=VCC or GND Output in High-Impedance State VIN = VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0µA VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA
ICC
Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
5.5
4.0
40
160
µA
∆ICC
≥-55°C
25°C to 125°C 2.4
mA
5.5
2.9
NOTE: Total Supply Current = ICC + ∑∆ICC
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IN74HCT240A
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit Symbol Parameter 25 °C to -55°C 20 28 25 12 10 15 ≤85°C ≤125°C Unit
tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tTLH, tTHL CIN COUT
Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Enable Output)
25 35 31 15 10 15
30 42 38 18 10 15
ns ns ns ns pF pF
Typical @25°C,VCC=5.0 V 55 pF
CPD
Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
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IN74HCT240A
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/8 of the Device)
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IN74HCT240A
N SUFFIX PLASTIC DIP (MS - 001AD)
A
Dimension, mm
20 11 B 1 10
Symbol A B C
MIN 24.89 6.1
MAX 26.92 7.11 5.33
F
L
D F
0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38
0.56 1.78
C -T- SEATING
PLANE
G H
H J
N G D 0.25 (0.010) M T K M
J K L M N
.