ADSP-21065L

a SUMMARY High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral I2S Support, for Eight Simultaneous Receive and Transmit Channels KEY FEATURES 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory Two External Port, DMA Channels and Eight Serial Port, DMA Channels DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External Memory (@ 66 MHz) 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package 3.3 Volt Operation Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats 32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators Parallel Computations Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT Butterfly Computation 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles) DUAL-PORTED SRAM BLOCK 1 CORE PROCESSOR INSTRUCTION CACHE 32 ؋...