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DPS128C32BV3 Dataheets PDF



Part Number DPS128C32BV3
Manufacturers Dense-Pac Microsystems
Logo Dense-Pac Microsystems
Description 512kx8 High Speed CMOS SRAM
Datasheet DPS128C32BV3 DatasheetDPS128C32BV3 Datasheet (PDF)

4 Megabit High Speed CMOS SRAM DPS128C32BV3 DESCRIPTION: The DPS128C32BV3 ‘’VERSA-STACK’’ module is a revolutionary new high speed memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 4 Megabits of SRAM in a package envelope of 1.090 x 1.090 x 0.300 inches. The DPS128C32BV3 contains four individual 128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs making the module suitable for commercial,.

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4 Megabit High Speed CMOS SRAM DPS128C32BV3 DESCRIPTION: The DPS128C32BV3 ‘’VERSA-STACK’’ module is a revolutionary new high speed memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 4 Megabits of SRAM in a package envelope of 1.090 x 1.090 x 0.300 inches. The DPS128C32BV3 contains four individual 128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs making the module suitable for commercial, industrial and military applications. By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or hybrid techniques. w w w PIN-OUT DIAGRAM * Commercial only. .D at PIN NAMES A0 - A16 I/O0 - I/O31 CE0 - CE3 WE0 - WE3 OE VDD VSS N.C. aS he Address Inputs Data Input/Output Chip Enables Write Enables Output Enable Power (+5V) Ground No Connect 30A044-28 REV. F et 4U This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 .c om www.DataSheet4U.com FEATURES: • Organizations Available: 128K x 32, 256K x 16, or 512K x 8 • Access Times: 20, 25, 30, 35, 45ns • Fully Static Operation - No clock or refresh required • Single +5V Power Supply, ±10% Tolerance • TTL Compatible • Common Data Inputs and Outputs • Low Data Retention Voltage: 2.0V min. • 66-Pin PGA ‘’VERSA-STACK’’ Package FUNCTIONAL BLOCK DIAGRAM DPS128C32BV3 RECOMMENDED OPERATING RANGE 3 Symbol Characteristic Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V VIH Input HIGH Voltage 2.2 VDD+0.3 V VIL Input LOW Voltage -0.52 0.8 V M/B -55 +25 +125 Operating o TA C I -40 +25 +85 Temperature C 0 +25 +70 Mode Not Selected DOUT Disable Read Write H = HIGH H L L L Dense-Pac Microsystems, Inc. TRUTH TABLE CE WE X H H L L = LOW OE X H L X Supply I/O Pin Current High-Z Standby High-Z Active DOUT Active DIN Active X = Don’t Care DC OUTPUT CHARACTERISTICS Symbol Parameter VOH HIGH Voltage VOL LOW Voltage Conditions Min. Max. Unit IOH= -4.0mA 2.4 V IOL=8.0mA 0.4 V ABSOLUTE MAXIMUM RATINGS 3 Symbol TSTC TBIAS VDD VI/O Parameter Storage Temperature Temperature Under Bias Supply Voltage 1 Input/Output Voltage 1 Value Unit -65 to +150 °C -55 to +125 °C -0.5 to +7.0 °C -0.5 to VDD+0.5 V CAPACITANCE 4: TA = 25°C, F = 1.0MHz Symbol CADR CCE CWE COE CI/O Parameter Address Input Chip Enable Write Enable Output Enable Data Input/Output Max. 50 20 50 50 30 Unit pF Condition VIN2 = 0V DC OPERATING CHARACTERISTICS: Over operating ranges Symbol IIN IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Characteristics Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current (CMOS) Standby Current (TTL) Data Retention Supply Current (3V) Data Retention Supply Current (2V) Output Low Voltage Output High Voltage Test Conditions VIN = 0V to VDD VI/O = 0V to VDD, CE or OE = VIH, or WE = VIL X8 Cycle=min., Duty=100%, X16 IOUT = 0mA X32 VIN ≥ VDD -0.2V or VIN ≤ VSS +0.2V, CE ≥ VDD -0.2V CE = VIH VDR = 3V, CE ≥ VDR -0.2V VDR = 2V, CE ≥ VDR -0.2V IOUT = 8.0mA IOUT = -4.0mA Typ. (†) 175 250 400 1.6 100 0.28 0.14 2.4 C Min. Max. Min. I Max. Min. M Max. Unit µA µA mA mA mA mA mA V V -20 -10 +20 +10 230 340 560 20 120 1.6 1.0 0.4 -20 -10 +20 +10 245 350 560 20 140 2.4 1.6 -20 -10 +20 +10 265 390 640 40 140 8.0 7.2 2.4 0.4 2.4 0.4 † Typical measurements made at +25oC, Cycle = min., VDD = 5.0V. 2 30A044-28 REV. F Dense-Pac Microsystems, Inc. DPS128C32BV3 OUTPUT LOAD Load 1 2 CL 30pF 5pF Parameters Measured except tLZ, tHZ, tOHZ, tOLZ,and tWHZ tLZ, tHZ, tOHZ, tOLZ, and tWHZ Figure 1. Output Load * Including Probe and Jig Capacitance. +5V 480Ω DOUT AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels 0V to 3.0V 5ns 1.5V CL* 255Ω AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol 1 2 3 4 5 6 7 8 9 tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH Parameter Read Cycle Time Address Access Time CE to Output Valid Output Enable to Output Valid CE to Output in LOW-Z 4, 5 Output Enable to Output in LOW-Z 4, 5 CE to Output in HIGH-Z 4, 5 Output Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change 20ns** Min. Max. 25ns Min. Max. 30ns Min. Max. 35ns Min. Max. 45ns Min. Max. Unit ns ns ns ns ns ns ns ns ns 20 3 0 3 20 20 8 10 8 25 3 0 3 25 25 10 12 10 30 3 0 3 30 30 15 15 15 35 3 0 3 35 35 20 20 20 45 3 0 3 45 45 25 25 25 ** Available in Commercial Only. AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE6, 7: Over operating ranges No. Symbol 10 11 12 13 14 15 16 17 18 19 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW Parameter Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-Up Time *** Write Pulse Width Write Recovery Time .


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