Self Refresh Cycle
HM514260C, HM51S4260C Series
* WE, OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore
some care needs to be taken on the refresh.
1. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instead of tRP.
2. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles
of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately
after exiting from and before entering into the self refresh mode.
3. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh