Document
HM514260C Series HM51S4260C Series
262,144-word × 16-bit Dynamic Random Access Memory
ADE-203-260A (Z) Rev. 1.0 Jun. 12, 1995
Description
The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation.
Features
• • • Single 5 V (±10%) (HM51(S)4260C-6/7/8) (±5%) (HM51(S)4260C-6R) High speed — Access time: 60 ns/70 ns/80 ns (max) Low power dissipation — Active mode: 825 mW/788 mW/770 mW/688 mW (max) — Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8) 10.5 mW (max) (HM51(S)4260C-6R) 1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4260C-6R) Fast page mode capability 512 refresh cycles: 8 ms 128 ms (L-version) 2 CAS -byte control 2 variations of refresh — RAS -only refresh — CAS -before-RAS refresh Battery backup operation (L-version) Self refresh operation (HM51S4260C)
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HM514260C, HM51S4260C Series
Ordering Information
Type No. HM514260CJ-6 HM514260CJ-6R HM514260CJ-7 HM514260CJ-8 HM514260CLJ-6 HM514260CLJ-6R HM514260CLJ-7 HM514260CLJ-8 HM51S4260CJ-6 HM51S4260CJ-6R HM51S4260CJ-7 HM51S4260CJ-8 HM51S4260CLJ-6 HM51S4260CLJ-6R HM51S4260CLJ-7 HM51S4260CLJ-8 HM514260CTT-6 HM514260CTT-6R HM514260CTT-7 HM514260CTT-8 HM514260CLTT-6 HM514260CLTT-6R HM514260CLTT-7 HM514260CLTT-8 HM51S4260CTT-6 HM51S4260CTT-6R HM51S4260CTT-7 HM51S4260CTT-8 HM51S4260CLTT-6 HM51S4260CLTT-6R HM51S4260CLTT-7 HM51S4260CLTT-8 Access Time 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 400-mill 44-pin plastic TSOP II (TTP-44/40DB) Package 400-mill 40-pin plastic SOJ (CP-40DA)
2
HM514260C, HM51S4260C Series
Pin Arrangement
HM514260CJ/CLJ Series HM51S4260CJ/CLJ Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
HM514260CTT/CLTT Series HM51S4260CTT/CLTT Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8
(Top view)
NC NC WE RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
(Top view)
Pin Description
Pin Name A0 to A8 Function Address input – Row address – Column address – Refresh address Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground No connection A0 to A8 A0 to A8 A0 to A8
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
3
I/O5
I/O7 I/O6 I/O4
WE
I/O5 Buffer I/O4 Buffer I/O6 Buffer I/O7 Buffer
RAS
Row Decoder
Block Diagram
Row Decoder
256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder
Row Decoder I/O3 I/O3 Buffer
Selector
Selector
I/O Bus & Column Decoder
Address
I/O2
I/O2 Buffer
256 k Memory Array Mat
Row Row Decoder Decoder
Row Row Decoder Decoder
256 k Memory Array Mat
I/O1 I/O1 Buffer
Selector
Selector
I/O Bus & Column Decoder
Row Decoder
HM514260C, HM51S4260C Series
A0,A1,A2,A3
256 k Memory Array Mat
I/O0 I/O0 Buffer
256 k Memory Array Mat
Peripheral Circuit
4
I/O15 I/O15 Buffer Row Decoder I/O14 I/O14 Buffer
Peripheral Circuit
Peripheral Circuit
Row Decoder
256 k Memory Array Mat
256 k Memory Array Mat
Address A4,A5
Selector
Selector
I/O Bus & Column Decoder
I/O Bus & Column Decoder 256 k Memory Array Mat
I/O13 I/O13 Buffer
256 k Memory Array Mat
Row Row Decoder Decoder
Row Row Decoder Decoder
A6,A7,A8
256 k Memory Array Mat
256 k Memory Array Mat
Selector
Selector
I/O Bus & Column Decoder
Row Decoder
I/O Bus & Column Decoder
I/O12 I/O12 Buffer Row Decoder
256 k Memory Array Mat
256 k Memory Array Mat
I/O11 Buffer I/O9 Buffer I/O8 Buffer
I/O10 I/O10 Buffer
I/O11
I/O8
I/O9
LCAS
UCAS OE
HM514260C, HM51S4260C Series
Operation Mode
The HM51(S)4260C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read- modify-write cycle 5. RAS -only refresh cycle 6. CAS -before-RAS refresh cycle 7. Self refresh cycle(HM51S4260C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read- modify-write cycle
Inputs RAS H H L L L L L H to L LCAS H L L L L L H H L L L L L L L.